lpc82x_pac/i2c0/
mstctl.rs

1#[doc = "Register `MSTCTL` reader"]
2pub struct R(crate::R<MSTCTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MSTCTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MSTCTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MSTCTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MSTCTL` writer"]
17pub struct W(crate::W<MSTCTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MSTCTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MSTCTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MSTCTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Master Continue.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum MSTCONTINUE_A {
40    #[doc = "0: No effect."]
41    NO_EFFECT = 0,
42    #[doc = "1: Informs the Master function to continue to the next operation."]
43    CONTINUE = 1,
44}
45impl From<MSTCONTINUE_A> for bool {
46    #[inline(always)]
47    fn from(variant: MSTCONTINUE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `MSTCONTINUE` reader - Master Continue."]
52pub struct MSTCONTINUE_R(crate::FieldReader<bool, MSTCONTINUE_A>);
53impl MSTCONTINUE_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        MSTCONTINUE_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> MSTCONTINUE_A {
60        match self.bits {
61            false => MSTCONTINUE_A::NO_EFFECT,
62            true => MSTCONTINUE_A::CONTINUE,
63        }
64    }
65    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
66    #[inline(always)]
67    pub fn is_no_effect(&self) -> bool {
68        **self == MSTCONTINUE_A::NO_EFFECT
69    }
70    #[doc = "Checks if the value of the field is `CONTINUE`"]
71    #[inline(always)]
72    pub fn is_continue(&self) -> bool {
73        **self == MSTCONTINUE_A::CONTINUE
74    }
75}
76impl core::ops::Deref for MSTCONTINUE_R {
77    type Target = crate::FieldReader<bool, MSTCONTINUE_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `MSTCONTINUE` writer - Master Continue."]
84pub struct MSTCONTINUE_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> MSTCONTINUE_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: MSTCONTINUE_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "No effect."]
94    #[inline(always)]
95    pub fn no_effect(self) -> &'a mut W {
96        self.variant(MSTCONTINUE_A::NO_EFFECT)
97    }
98    #[doc = "Informs the Master function to continue to the next operation."]
99    #[inline(always)]
100    pub fn continue_(self) -> &'a mut W {
101        self.variant(MSTCONTINUE_A::CONTINUE)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Master Start control.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum MSTSTART_A {
123    #[doc = "0: No effect."]
124    NO_EFFECT = 0,
125    #[doc = "1: Start. A Start will be generated on the I2C bus at the next allowed time."]
126    START = 1,
127}
128impl From<MSTSTART_A> for bool {
129    #[inline(always)]
130    fn from(variant: MSTSTART_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `MSTSTART` reader - Master Start control."]
135pub struct MSTSTART_R(crate::FieldReader<bool, MSTSTART_A>);
136impl MSTSTART_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        MSTSTART_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> MSTSTART_A {
143        match self.bits {
144            false => MSTSTART_A::NO_EFFECT,
145            true => MSTSTART_A::START,
146        }
147    }
148    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
149    #[inline(always)]
150    pub fn is_no_effect(&self) -> bool {
151        **self == MSTSTART_A::NO_EFFECT
152    }
153    #[doc = "Checks if the value of the field is `START`"]
154    #[inline(always)]
155    pub fn is_start(&self) -> bool {
156        **self == MSTSTART_A::START
157    }
158}
159impl core::ops::Deref for MSTSTART_R {
160    type Target = crate::FieldReader<bool, MSTSTART_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `MSTSTART` writer - Master Start control."]
167pub struct MSTSTART_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> MSTSTART_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: MSTSTART_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "No effect."]
177    #[inline(always)]
178    pub fn no_effect(self) -> &'a mut W {
179        self.variant(MSTSTART_A::NO_EFFECT)
180    }
181    #[doc = "Start. A Start will be generated on the I2C bus at the next allowed time."]
182    #[inline(always)]
183    pub fn start(self) -> &'a mut W {
184        self.variant(MSTSTART_A::START)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200        self.w
201    }
202}
203#[doc = "Master Stop control.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum MSTSTOP_A {
206    #[doc = "0: No effect."]
207    NO_EFFECT = 0,
208    #[doc = "1: Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode)."]
209    STOP = 1,
210}
211impl From<MSTSTOP_A> for bool {
212    #[inline(always)]
213    fn from(variant: MSTSTOP_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `MSTSTOP` reader - Master Stop control."]
218pub struct MSTSTOP_R(crate::FieldReader<bool, MSTSTOP_A>);
219impl MSTSTOP_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        MSTSTOP_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> MSTSTOP_A {
226        match self.bits {
227            false => MSTSTOP_A::NO_EFFECT,
228            true => MSTSTOP_A::STOP,
229        }
230    }
231    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
232    #[inline(always)]
233    pub fn is_no_effect(&self) -> bool {
234        **self == MSTSTOP_A::NO_EFFECT
235    }
236    #[doc = "Checks if the value of the field is `STOP`"]
237    #[inline(always)]
238    pub fn is_stop(&self) -> bool {
239        **self == MSTSTOP_A::STOP
240    }
241}
242impl core::ops::Deref for MSTSTOP_R {
243    type Target = crate::FieldReader<bool, MSTSTOP_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `MSTSTOP` writer - Master Stop control."]
250pub struct MSTSTOP_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> MSTSTOP_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: MSTSTOP_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "No effect."]
260    #[inline(always)]
261    pub fn no_effect(self) -> &'a mut W {
262        self.variant(MSTSTOP_A::NO_EFFECT)
263    }
264    #[doc = "Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode)."]
265    #[inline(always)]
266    pub fn stop(self) -> &'a mut W {
267        self.variant(MSTSTOP_A::STOP)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
283        self.w
284    }
285}
286#[doc = "Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288pub enum MSTDMA_A {
289    #[doc = "0: Disable. No DMA requests are generated for master operation."]
290    DISABLED = 0,
291    #[doc = "1: Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically."]
292    ENABLED = 1,
293}
294impl From<MSTDMA_A> for bool {
295    #[inline(always)]
296    fn from(variant: MSTDMA_A) -> Self {
297        variant as u8 != 0
298    }
299}
300#[doc = "Field `MSTDMA` reader - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
301pub struct MSTDMA_R(crate::FieldReader<bool, MSTDMA_A>);
302impl MSTDMA_R {
303    pub(crate) fn new(bits: bool) -> Self {
304        MSTDMA_R(crate::FieldReader::new(bits))
305    }
306    #[doc = r"Get enumerated values variant"]
307    #[inline(always)]
308    pub fn variant(&self) -> MSTDMA_A {
309        match self.bits {
310            false => MSTDMA_A::DISABLED,
311            true => MSTDMA_A::ENABLED,
312        }
313    }
314    #[doc = "Checks if the value of the field is `DISABLED`"]
315    #[inline(always)]
316    pub fn is_disabled(&self) -> bool {
317        **self == MSTDMA_A::DISABLED
318    }
319    #[doc = "Checks if the value of the field is `ENABLED`"]
320    #[inline(always)]
321    pub fn is_enabled(&self) -> bool {
322        **self == MSTDMA_A::ENABLED
323    }
324}
325impl core::ops::Deref for MSTDMA_R {
326    type Target = crate::FieldReader<bool, MSTDMA_A>;
327    #[inline(always)]
328    fn deref(&self) -> &Self::Target {
329        &self.0
330    }
331}
332#[doc = "Field `MSTDMA` writer - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
333pub struct MSTDMA_W<'a> {
334    w: &'a mut W,
335}
336impl<'a> MSTDMA_W<'a> {
337    #[doc = r"Writes `variant` to the field"]
338    #[inline(always)]
339    pub fn variant(self, variant: MSTDMA_A) -> &'a mut W {
340        self.bit(variant.into())
341    }
342    #[doc = "Disable. No DMA requests are generated for master operation."]
343    #[inline(always)]
344    pub fn disabled(self) -> &'a mut W {
345        self.variant(MSTDMA_A::DISABLED)
346    }
347    #[doc = "Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically."]
348    #[inline(always)]
349    pub fn enabled(self) -> &'a mut W {
350        self.variant(MSTDMA_A::ENABLED)
351    }
352    #[doc = r"Sets the field bit"]
353    #[inline(always)]
354    pub fn set_bit(self) -> &'a mut W {
355        self.bit(true)
356    }
357    #[doc = r"Clears the field bit"]
358    #[inline(always)]
359    pub fn clear_bit(self) -> &'a mut W {
360        self.bit(false)
361    }
362    #[doc = r"Writes raw bits to the field"]
363    #[inline(always)]
364    pub fn bit(self, value: bool) -> &'a mut W {
365        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
366        self.w
367    }
368}
369impl R {
370    #[doc = "Bit 0 - Master Continue."]
371    #[inline(always)]
372    pub fn mstcontinue(&self) -> MSTCONTINUE_R {
373        MSTCONTINUE_R::new((self.bits & 0x01) != 0)
374    }
375    #[doc = "Bit 1 - Master Start control."]
376    #[inline(always)]
377    pub fn mststart(&self) -> MSTSTART_R {
378        MSTSTART_R::new(((self.bits >> 1) & 0x01) != 0)
379    }
380    #[doc = "Bit 2 - Master Stop control."]
381    #[inline(always)]
382    pub fn mststop(&self) -> MSTSTOP_R {
383        MSTSTOP_R::new(((self.bits >> 2) & 0x01) != 0)
384    }
385    #[doc = "Bit 3 - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
386    #[inline(always)]
387    pub fn mstdma(&self) -> MSTDMA_R {
388        MSTDMA_R::new(((self.bits >> 3) & 0x01) != 0)
389    }
390}
391impl W {
392    #[doc = "Bit 0 - Master Continue."]
393    #[inline(always)]
394    pub fn mstcontinue(&mut self) -> MSTCONTINUE_W {
395        MSTCONTINUE_W { w: self }
396    }
397    #[doc = "Bit 1 - Master Start control."]
398    #[inline(always)]
399    pub fn mststart(&mut self) -> MSTSTART_W {
400        MSTSTART_W { w: self }
401    }
402    #[doc = "Bit 2 - Master Stop control."]
403    #[inline(always)]
404    pub fn mststop(&mut self) -> MSTSTOP_W {
405        MSTSTOP_W { w: self }
406    }
407    #[doc = "Bit 3 - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write."]
408    #[inline(always)]
409    pub fn mstdma(&mut self) -> MSTDMA_W {
410        MSTDMA_W { w: self }
411    }
412    #[doc = "Writes raw bits to the register."]
413    #[inline(always)]
414    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
415        self.0.bits(bits);
416        self
417    }
418}
419#[doc = "Master control register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mstctl](index.html) module"]
420pub struct MSTCTL_SPEC;
421impl crate::RegisterSpec for MSTCTL_SPEC {
422    type Ux = u32;
423}
424#[doc = "`read()` method returns [mstctl::R](R) reader structure"]
425impl crate::Readable for MSTCTL_SPEC {
426    type Reader = R;
427}
428#[doc = "`write(|w| ..)` method takes [mstctl::W](W) writer structure"]
429impl crate::Writable for MSTCTL_SPEC {
430    type Writer = W;
431}
432#[doc = "`reset()` method sets MSTCTL to value 0"]
433impl crate::Resettable for MSTCTL_SPEC {
434    #[inline(always)]
435    fn reset_value() -> Self::Ux {
436        0
437    }
438}
lpc82x_pac/i2c0/mstctl.rs

lpc82x_pac/i2c0/
mstctl.rs
