lpc82x_pac/dma0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "DMA controller master enable.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum ENABLE_A {
40    #[doc = "0: Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled."]
41    DISABLED = 0,
42    #[doc = "1: Enabled. The DMA controller is enabled."]
43    ENABLED = 1,
44}
45impl From<ENABLE_A> for bool {
46    #[inline(always)]
47    fn from(variant: ENABLE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `ENABLE` reader - DMA controller master enable."]
52pub struct ENABLE_R(crate::FieldReader<bool, ENABLE_A>);
53impl ENABLE_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        ENABLE_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> ENABLE_A {
60        match self.bits {
61            false => ENABLE_A::DISABLED,
62            true => ENABLE_A::ENABLED,
63        }
64    }
65    #[doc = "Checks if the value of the field is `DISABLED`"]
66    #[inline(always)]
67    pub fn is_disabled(&self) -> bool {
68        **self == ENABLE_A::DISABLED
69    }
70    #[doc = "Checks if the value of the field is `ENABLED`"]
71    #[inline(always)]
72    pub fn is_enabled(&self) -> bool {
73        **self == ENABLE_A::ENABLED
74    }
75}
76impl core::ops::Deref for ENABLE_R {
77    type Target = crate::FieldReader<bool, ENABLE_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `ENABLE` writer - DMA controller master enable."]
84pub struct ENABLE_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> ENABLE_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: ENABLE_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled."]
94    #[inline(always)]
95    pub fn disabled(self) -> &'a mut W {
96        self.variant(ENABLE_A::DISABLED)
97    }
98    #[doc = "Enabled. The DMA controller is enabled."]
99    #[inline(always)]
100    pub fn enabled(self) -> &'a mut W {
101        self.variant(ENABLE_A::ENABLED)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120impl R {
121    #[doc = "Bit 0 - DMA controller master enable."]
122    #[inline(always)]
123    pub fn enable(&self) -> ENABLE_R {
124        ENABLE_R::new((self.bits & 0x01) != 0)
125    }
126}
127impl W {
128    #[doc = "Bit 0 - DMA controller master enable."]
129    #[inline(always)]
130    pub fn enable(&mut self) -> ENABLE_W {
131        ENABLE_W { w: self }
132    }
133    #[doc = "Writes raw bits to the register."]
134    #[inline(always)]
135    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
136        self.0.bits(bits);
137        self
138    }
139}
140#[doc = "DMA control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
141pub struct CTRL_SPEC;
142impl crate::RegisterSpec for CTRL_SPEC {
143    type Ux = u32;
144}
145#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
146impl crate::Readable for CTRL_SPEC {
147    type Reader = R;
148}
149#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
150impl crate::Writable for CTRL_SPEC {
151    type Writer = W;
152}
153#[doc = "`reset()` method sets CTRL to value 0"]
154impl crate::Resettable for CTRL_SPEC {
155    #[inline(always)]
156    fn reset_value() -> Self::Ux {
157        0
158    }
159}
lpc82x_pac/dma0/ctrl.rs

lpc82x_pac/dma0/
ctrl.rs
