lpc82x_pac/dma0/channel/
ctlstat.rs

1#[doc = "Register `CTLSTAT` reader"]
2pub struct R(crate::R<CTLSTAT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTLSTAT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTLSTAT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTLSTAT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.\n\nValue on reset: 0"]
17#[derive(Clone, Copy, Debug, PartialEq)]
18pub enum VALIDPENDING_A {
19    #[doc = "0: No effect. No effect on DMA operation."]
20    NO_EFFECT = 0,
21    #[doc = "1: Valid pending."]
22    VALID_PENDING = 1,
23}
24impl From<VALIDPENDING_A> for bool {
25    #[inline(always)]
26    fn from(variant: VALIDPENDING_A) -> Self {
27        variant as u8 != 0
28    }
29}
30#[doc = "Field `VALIDPENDING` reader - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."]
31pub struct VALIDPENDING_R(crate::FieldReader<bool, VALIDPENDING_A>);
32impl VALIDPENDING_R {
33    pub(crate) fn new(bits: bool) -> Self {
34        VALIDPENDING_R(crate::FieldReader::new(bits))
35    }
36    #[doc = r"Get enumerated values variant"]
37    #[inline(always)]
38    pub fn variant(&self) -> VALIDPENDING_A {
39        match self.bits {
40            false => VALIDPENDING_A::NO_EFFECT,
41            true => VALIDPENDING_A::VALID_PENDING,
42        }
43    }
44    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
45    #[inline(always)]
46    pub fn is_no_effect(&self) -> bool {
47        **self == VALIDPENDING_A::NO_EFFECT
48    }
49    #[doc = "Checks if the value of the field is `VALID_PENDING`"]
50    #[inline(always)]
51    pub fn is_valid_pending(&self) -> bool {
52        **self == VALIDPENDING_A::VALID_PENDING
53    }
54}
55impl core::ops::Deref for VALIDPENDING_R {
56    type Target = crate::FieldReader<bool, VALIDPENDING_A>;
57    #[inline(always)]
58    fn deref(&self) -> &Self::Target {
59        &self.0
60    }
61}
62#[doc = "Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq)]
64pub enum TRIG_A {
65    #[doc = "0: Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out."]
66    NOT_TRIGGERED = 0,
67    #[doc = "1: Triggered. The trigger for this DMA channel is set. DMA operations will be carried out."]
68    TRIGGERED = 1,
69}
70impl From<TRIG_A> for bool {
71    #[inline(always)]
72    fn from(variant: TRIG_A) -> Self {
73        variant as u8 != 0
74    }
75}
76#[doc = "Field `TRIG` reader - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."]
77pub struct TRIG_R(crate::FieldReader<bool, TRIG_A>);
78impl TRIG_R {
79    pub(crate) fn new(bits: bool) -> Self {
80        TRIG_R(crate::FieldReader::new(bits))
81    }
82    #[doc = r"Get enumerated values variant"]
83    #[inline(always)]
84    pub fn variant(&self) -> TRIG_A {
85        match self.bits {
86            false => TRIG_A::NOT_TRIGGERED,
87            true => TRIG_A::TRIGGERED,
88        }
89    }
90    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
91    #[inline(always)]
92    pub fn is_not_triggered(&self) -> bool {
93        **self == TRIG_A::NOT_TRIGGERED
94    }
95    #[doc = "Checks if the value of the field is `TRIGGERED`"]
96    #[inline(always)]
97    pub fn is_triggered(&self) -> bool {
98        **self == TRIG_A::TRIGGERED
99    }
100}
101impl core::ops::Deref for TRIG_R {
102    type Target = crate::FieldReader<bool, TRIG_A>;
103    #[inline(always)]
104    fn deref(&self) -> &Self::Target {
105        &self.0
106    }
107}
108impl R {
109    #[doc = "Bit 0 - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel."]
110    #[inline(always)]
111    pub fn validpending(&self) -> VALIDPENDING_R {
112        VALIDPENDING_R::new((self.bits & 0x01) != 0)
113    }
114    #[doc = "Bit 2 - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1."]
115    #[inline(always)]
116    pub fn trig(&self) -> TRIG_R {
117        TRIG_R::new(((self.bits >> 2) & 0x01) != 0)
118    }
119}
120#[doc = "Control and status register for DMA channel .\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctlstat](index.html) module"]
121pub struct CTLSTAT_SPEC;
122impl crate::RegisterSpec for CTLSTAT_SPEC {
123    type Ux = u32;
124}
125#[doc = "`read()` method returns [ctlstat::R](R) reader structure"]
126impl crate::Readable for CTLSTAT_SPEC {
127    type Reader = R;
128}
129#[doc = "`reset()` method sets CTLSTAT to value 0"]
130impl crate::Resettable for CTLSTAT_SPEC {
131    #[inline(always)]
132    fn reset_value() -> Self::Ux {
133        0
134    }
135}
lpc82x_pac/dma0/channel/ctlstat.rs

lpc82x_pac/dma0/channel/
ctlstat.rs
