lpc82x_pac/adc0/
inten.rs

1#[doc = "Register `INTEN` reader"]
2pub struct R(crate::R<INTEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTEN` writer"]
17pub struct W(crate::W<INTEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Sequence A interrupt enable.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum SEQA_INTEN_A {
40    #[doc = "0: Disabled. The sequence A interrupt/DMA trigger is disabled."]
41    DISABLED = 0,
42    #[doc = "1: Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register."]
43    ENABLED = 1,
44}
45impl From<SEQA_INTEN_A> for bool {
46    #[inline(always)]
47    fn from(variant: SEQA_INTEN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `SEQA_INTEN` reader - Sequence A interrupt enable."]
52pub struct SEQA_INTEN_R(crate::FieldReader<bool, SEQA_INTEN_A>);
53impl SEQA_INTEN_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        SEQA_INTEN_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> SEQA_INTEN_A {
60        match self.bits {
61            false => SEQA_INTEN_A::DISABLED,
62            true => SEQA_INTEN_A::ENABLED,
63        }
64    }
65    #[doc = "Checks if the value of the field is `DISABLED`"]
66    #[inline(always)]
67    pub fn is_disabled(&self) -> bool {
68        **self == SEQA_INTEN_A::DISABLED
69    }
70    #[doc = "Checks if the value of the field is `ENABLED`"]
71    #[inline(always)]
72    pub fn is_enabled(&self) -> bool {
73        **self == SEQA_INTEN_A::ENABLED
74    }
75}
76impl core::ops::Deref for SEQA_INTEN_R {
77    type Target = crate::FieldReader<bool, SEQA_INTEN_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `SEQA_INTEN` writer - Sequence A interrupt enable."]
84pub struct SEQA_INTEN_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> SEQA_INTEN_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: SEQA_INTEN_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "Disabled. The sequence A interrupt/DMA trigger is disabled."]
94    #[inline(always)]
95    pub fn disabled(self) -> &'a mut W {
96        self.variant(SEQA_INTEN_A::DISABLED)
97    }
98    #[doc = "Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register."]
99    #[inline(always)]
100    pub fn enabled(self) -> &'a mut W {
101        self.variant(SEQA_INTEN_A::ENABLED)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Sequence B interrupt enable.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum SEQB_INTEN_A {
123    #[doc = "0: Disabled. The sequence B interrupt/DMA trigger is disabled."]
124    DISABLED = 0,
125    #[doc = "1: Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register."]
126    ENABLED = 1,
127}
128impl From<SEQB_INTEN_A> for bool {
129    #[inline(always)]
130    fn from(variant: SEQB_INTEN_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `SEQB_INTEN` reader - Sequence B interrupt enable."]
135pub struct SEQB_INTEN_R(crate::FieldReader<bool, SEQB_INTEN_A>);
136impl SEQB_INTEN_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        SEQB_INTEN_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> SEQB_INTEN_A {
143        match self.bits {
144            false => SEQB_INTEN_A::DISABLED,
145            true => SEQB_INTEN_A::ENABLED,
146        }
147    }
148    #[doc = "Checks if the value of the field is `DISABLED`"]
149    #[inline(always)]
150    pub fn is_disabled(&self) -> bool {
151        **self == SEQB_INTEN_A::DISABLED
152    }
153    #[doc = "Checks if the value of the field is `ENABLED`"]
154    #[inline(always)]
155    pub fn is_enabled(&self) -> bool {
156        **self == SEQB_INTEN_A::ENABLED
157    }
158}
159impl core::ops::Deref for SEQB_INTEN_R {
160    type Target = crate::FieldReader<bool, SEQB_INTEN_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `SEQB_INTEN` writer - Sequence B interrupt enable."]
167pub struct SEQB_INTEN_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> SEQB_INTEN_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: SEQB_INTEN_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "Disabled. The sequence B interrupt/DMA trigger is disabled."]
177    #[inline(always)]
178    pub fn disabled(self) -> &'a mut W {
179        self.variant(SEQB_INTEN_A::DISABLED)
180    }
181    #[doc = "Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register."]
182    #[inline(always)]
183    pub fn enabled(self) -> &'a mut W {
184        self.variant(SEQB_INTEN_A::ENABLED)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200        self.w
201    }
202}
203#[doc = "Overrun interrupt enable.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum OVR_INTEN_A {
206    #[doc = "0: Disabled. The overrun interrupt is disabled."]
207    DISABLED = 0,
208    #[doc = "1: Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted."]
209    ENABLED = 1,
210}
211impl From<OVR_INTEN_A> for bool {
212    #[inline(always)]
213    fn from(variant: OVR_INTEN_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `OVR_INTEN` reader - Overrun interrupt enable."]
218pub struct OVR_INTEN_R(crate::FieldReader<bool, OVR_INTEN_A>);
219impl OVR_INTEN_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        OVR_INTEN_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> OVR_INTEN_A {
226        match self.bits {
227            false => OVR_INTEN_A::DISABLED,
228            true => OVR_INTEN_A::ENABLED,
229        }
230    }
231    #[doc = "Checks if the value of the field is `DISABLED`"]
232    #[inline(always)]
233    pub fn is_disabled(&self) -> bool {
234        **self == OVR_INTEN_A::DISABLED
235    }
236    #[doc = "Checks if the value of the field is `ENABLED`"]
237    #[inline(always)]
238    pub fn is_enabled(&self) -> bool {
239        **self == OVR_INTEN_A::ENABLED
240    }
241}
242impl core::ops::Deref for OVR_INTEN_R {
243    type Target = crate::FieldReader<bool, OVR_INTEN_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `OVR_INTEN` writer - Overrun interrupt enable."]
250pub struct OVR_INTEN_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> OVR_INTEN_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: OVR_INTEN_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "Disabled. The overrun interrupt is disabled."]
260    #[inline(always)]
261    pub fn disabled(self) -> &'a mut W {
262        self.variant(OVR_INTEN_A::DISABLED)
263    }
264    #[doc = "Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted."]
265    #[inline(always)]
266    pub fn enabled(self) -> &'a mut W {
267        self.variant(OVR_INTEN_A::ENABLED)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
283        self.w
284    }
285}
286#[doc = "Threshold comparison interrupt enable for channel 0.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288#[repr(u8)]
289pub enum ADCMPINTEN0_A {
290    #[doc = "0: Disabled."]
291    DISABLED = 0,
292    #[doc = "1: Outside threshold."]
293    OUTSIDE_THRESHOLD = 1,
294    #[doc = "2: Crossing threshold."]
295    CROSSING_THRESHOLD = 2,
296}
297impl From<ADCMPINTEN0_A> for u8 {
298    #[inline(always)]
299    fn from(variant: ADCMPINTEN0_A) -> Self {
300        variant as _
301    }
302}
303#[doc = "Field `ADCMPINTEN0` reader - Threshold comparison interrupt enable for channel 0."]
304pub struct ADCMPINTEN0_R(crate::FieldReader<u8, ADCMPINTEN0_A>);
305impl ADCMPINTEN0_R {
306    pub(crate) fn new(bits: u8) -> Self {
307        ADCMPINTEN0_R(crate::FieldReader::new(bits))
308    }
309    #[doc = r"Get enumerated values variant"]
310    #[inline(always)]
311    pub fn variant(&self) -> Option<ADCMPINTEN0_A> {
312        match self.bits {
313            0 => Some(ADCMPINTEN0_A::DISABLED),
314            1 => Some(ADCMPINTEN0_A::OUTSIDE_THRESHOLD),
315            2 => Some(ADCMPINTEN0_A::CROSSING_THRESHOLD),
316            _ => None,
317        }
318    }
319    #[doc = "Checks if the value of the field is `DISABLED`"]
320    #[inline(always)]
321    pub fn is_disabled(&self) -> bool {
322        **self == ADCMPINTEN0_A::DISABLED
323    }
324    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
325    #[inline(always)]
326    pub fn is_outside_threshold(&self) -> bool {
327        **self == ADCMPINTEN0_A::OUTSIDE_THRESHOLD
328    }
329    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
330    #[inline(always)]
331    pub fn is_crossing_threshold(&self) -> bool {
332        **self == ADCMPINTEN0_A::CROSSING_THRESHOLD
333    }
334}
335impl core::ops::Deref for ADCMPINTEN0_R {
336    type Target = crate::FieldReader<u8, ADCMPINTEN0_A>;
337    #[inline(always)]
338    fn deref(&self) -> &Self::Target {
339        &self.0
340    }
341}
342#[doc = "Field `ADCMPINTEN0` writer - Threshold comparison interrupt enable for channel 0."]
343pub struct ADCMPINTEN0_W<'a> {
344    w: &'a mut W,
345}
346impl<'a> ADCMPINTEN0_W<'a> {
347    #[doc = r"Writes `variant` to the field"]
348    #[inline(always)]
349    pub fn variant(self, variant: ADCMPINTEN0_A) -> &'a mut W {
350        unsafe { self.bits(variant.into()) }
351    }
352    #[doc = "Disabled."]
353    #[inline(always)]
354    pub fn disabled(self) -> &'a mut W {
355        self.variant(ADCMPINTEN0_A::DISABLED)
356    }
357    #[doc = "Outside threshold."]
358    #[inline(always)]
359    pub fn outside_threshold(self) -> &'a mut W {
360        self.variant(ADCMPINTEN0_A::OUTSIDE_THRESHOLD)
361    }
362    #[doc = "Crossing threshold."]
363    #[inline(always)]
364    pub fn crossing_threshold(self) -> &'a mut W {
365        self.variant(ADCMPINTEN0_A::CROSSING_THRESHOLD)
366    }
367    #[doc = r"Writes raw bits to the field"]
368    #[inline(always)]
369    pub unsafe fn bits(self, value: u8) -> &'a mut W {
370        self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3);
371        self.w
372    }
373}
374#[doc = "Channel 1 threshold comparison interrupt enable.\n\nValue on reset: 0"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376#[repr(u8)]
377pub enum ADCMPINTEN1_A {
378    #[doc = "0: Disabled."]
379    DISABLED = 0,
380    #[doc = "1: Outside threshold."]
381    OUTSIDE_THRESHOLD = 1,
382    #[doc = "2: Crossing threshold."]
383    CROSSING_THRESHOLD = 2,
384}
385impl From<ADCMPINTEN1_A> for u8 {
386    #[inline(always)]
387    fn from(variant: ADCMPINTEN1_A) -> Self {
388        variant as _
389    }
390}
391#[doc = "Field `ADCMPINTEN1` reader - Channel 1 threshold comparison interrupt enable."]
392pub struct ADCMPINTEN1_R(crate::FieldReader<u8, ADCMPINTEN1_A>);
393impl ADCMPINTEN1_R {
394    pub(crate) fn new(bits: u8) -> Self {
395        ADCMPINTEN1_R(crate::FieldReader::new(bits))
396    }
397    #[doc = r"Get enumerated values variant"]
398    #[inline(always)]
399    pub fn variant(&self) -> Option<ADCMPINTEN1_A> {
400        match self.bits {
401            0 => Some(ADCMPINTEN1_A::DISABLED),
402            1 => Some(ADCMPINTEN1_A::OUTSIDE_THRESHOLD),
403            2 => Some(ADCMPINTEN1_A::CROSSING_THRESHOLD),
404            _ => None,
405        }
406    }
407    #[doc = "Checks if the value of the field is `DISABLED`"]
408    #[inline(always)]
409    pub fn is_disabled(&self) -> bool {
410        **self == ADCMPINTEN1_A::DISABLED
411    }
412    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
413    #[inline(always)]
414    pub fn is_outside_threshold(&self) -> bool {
415        **self == ADCMPINTEN1_A::OUTSIDE_THRESHOLD
416    }
417    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
418    #[inline(always)]
419    pub fn is_crossing_threshold(&self) -> bool {
420        **self == ADCMPINTEN1_A::CROSSING_THRESHOLD
421    }
422}
423impl core::ops::Deref for ADCMPINTEN1_R {
424    type Target = crate::FieldReader<u8, ADCMPINTEN1_A>;
425    #[inline(always)]
426    fn deref(&self) -> &Self::Target {
427        &self.0
428    }
429}
430#[doc = "Field `ADCMPINTEN1` writer - Channel 1 threshold comparison interrupt enable."]
431pub struct ADCMPINTEN1_W<'a> {
432    w: &'a mut W,
433}
434impl<'a> ADCMPINTEN1_W<'a> {
435    #[doc = r"Writes `variant` to the field"]
436    #[inline(always)]
437    pub fn variant(self, variant: ADCMPINTEN1_A) -> &'a mut W {
438        unsafe { self.bits(variant.into()) }
439    }
440    #[doc = "Disabled."]
441    #[inline(always)]
442    pub fn disabled(self) -> &'a mut W {
443        self.variant(ADCMPINTEN1_A::DISABLED)
444    }
445    #[doc = "Outside threshold."]
446    #[inline(always)]
447    pub fn outside_threshold(self) -> &'a mut W {
448        self.variant(ADCMPINTEN1_A::OUTSIDE_THRESHOLD)
449    }
450    #[doc = "Crossing threshold."]
451    #[inline(always)]
452    pub fn crossing_threshold(self) -> &'a mut W {
453        self.variant(ADCMPINTEN1_A::CROSSING_THRESHOLD)
454    }
455    #[doc = r"Writes raw bits to the field"]
456    #[inline(always)]
457    pub unsafe fn bits(self, value: u8) -> &'a mut W {
458        self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
459        self.w
460    }
461}
462#[doc = "Channel 2 threshold comparison interrupt enable.\n\nValue on reset: 0"]
463#[derive(Clone, Copy, Debug, PartialEq)]
464#[repr(u8)]
465pub enum ADCMPINTEN2_A {
466    #[doc = "0: Disabled."]
467    DISABLED = 0,
468    #[doc = "1: Outside threshold."]
469    OUTSIDE_THRESHOLD = 1,
470    #[doc = "2: Crossing threshold."]
471    CROSSING_THRESHOLD = 2,
472}
473impl From<ADCMPINTEN2_A> for u8 {
474    #[inline(always)]
475    fn from(variant: ADCMPINTEN2_A) -> Self {
476        variant as _
477    }
478}
479#[doc = "Field `ADCMPINTEN2` reader - Channel 2 threshold comparison interrupt enable."]
480pub struct ADCMPINTEN2_R(crate::FieldReader<u8, ADCMPINTEN2_A>);
481impl ADCMPINTEN2_R {
482    pub(crate) fn new(bits: u8) -> Self {
483        ADCMPINTEN2_R(crate::FieldReader::new(bits))
484    }
485    #[doc = r"Get enumerated values variant"]
486    #[inline(always)]
487    pub fn variant(&self) -> Option<ADCMPINTEN2_A> {
488        match self.bits {
489            0 => Some(ADCMPINTEN2_A::DISABLED),
490            1 => Some(ADCMPINTEN2_A::OUTSIDE_THRESHOLD),
491            2 => Some(ADCMPINTEN2_A::CROSSING_THRESHOLD),
492            _ => None,
493        }
494    }
495    #[doc = "Checks if the value of the field is `DISABLED`"]
496    #[inline(always)]
497    pub fn is_disabled(&self) -> bool {
498        **self == ADCMPINTEN2_A::DISABLED
499    }
500    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
501    #[inline(always)]
502    pub fn is_outside_threshold(&self) -> bool {
503        **self == ADCMPINTEN2_A::OUTSIDE_THRESHOLD
504    }
505    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
506    #[inline(always)]
507    pub fn is_crossing_threshold(&self) -> bool {
508        **self == ADCMPINTEN2_A::CROSSING_THRESHOLD
509    }
510}
511impl core::ops::Deref for ADCMPINTEN2_R {
512    type Target = crate::FieldReader<u8, ADCMPINTEN2_A>;
513    #[inline(always)]
514    fn deref(&self) -> &Self::Target {
515        &self.0
516    }
517}
518#[doc = "Field `ADCMPINTEN2` writer - Channel 2 threshold comparison interrupt enable."]
519pub struct ADCMPINTEN2_W<'a> {
520    w: &'a mut W,
521}
522impl<'a> ADCMPINTEN2_W<'a> {
523    #[doc = r"Writes `variant` to the field"]
524    #[inline(always)]
525    pub fn variant(self, variant: ADCMPINTEN2_A) -> &'a mut W {
526        unsafe { self.bits(variant.into()) }
527    }
528    #[doc = "Disabled."]
529    #[inline(always)]
530    pub fn disabled(self) -> &'a mut W {
531        self.variant(ADCMPINTEN2_A::DISABLED)
532    }
533    #[doc = "Outside threshold."]
534    #[inline(always)]
535    pub fn outside_threshold(self) -> &'a mut W {
536        self.variant(ADCMPINTEN2_A::OUTSIDE_THRESHOLD)
537    }
538    #[doc = "Crossing threshold."]
539    #[inline(always)]
540    pub fn crossing_threshold(self) -> &'a mut W {
541        self.variant(ADCMPINTEN2_A::CROSSING_THRESHOLD)
542    }
543    #[doc = r"Writes raw bits to the field"]
544    #[inline(always)]
545    pub unsafe fn bits(self, value: u8) -> &'a mut W {
546        self.w.bits = (self.w.bits & !(0x03 << 7)) | ((value as u32 & 0x03) << 7);
547        self.w
548    }
549}
550#[doc = "Channel 3 threshold comparison interrupt enable.\n\nValue on reset: 0"]
551#[derive(Clone, Copy, Debug, PartialEq)]
552#[repr(u8)]
553pub enum ADCMPINTEN3_A {
554    #[doc = "0: Disabled."]
555    DISABLED = 0,
556    #[doc = "1: Outside threshold."]
557    OUTSIDE_THRESHOLD = 1,
558    #[doc = "2: Crossing threshold."]
559    CROSSING_THRESHOLD = 2,
560}
561impl From<ADCMPINTEN3_A> for u8 {
562    #[inline(always)]
563    fn from(variant: ADCMPINTEN3_A) -> Self {
564        variant as _
565    }
566}
567#[doc = "Field `ADCMPINTEN3` reader - Channel 3 threshold comparison interrupt enable."]
568pub struct ADCMPINTEN3_R(crate::FieldReader<u8, ADCMPINTEN3_A>);
569impl ADCMPINTEN3_R {
570    pub(crate) fn new(bits: u8) -> Self {
571        ADCMPINTEN3_R(crate::FieldReader::new(bits))
572    }
573    #[doc = r"Get enumerated values variant"]
574    #[inline(always)]
575    pub fn variant(&self) -> Option<ADCMPINTEN3_A> {
576        match self.bits {
577            0 => Some(ADCMPINTEN3_A::DISABLED),
578            1 => Some(ADCMPINTEN3_A::OUTSIDE_THRESHOLD),
579            2 => Some(ADCMPINTEN3_A::CROSSING_THRESHOLD),
580            _ => None,
581        }
582    }
583    #[doc = "Checks if the value of the field is `DISABLED`"]
584    #[inline(always)]
585    pub fn is_disabled(&self) -> bool {
586        **self == ADCMPINTEN3_A::DISABLED
587    }
588    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
589    #[inline(always)]
590    pub fn is_outside_threshold(&self) -> bool {
591        **self == ADCMPINTEN3_A::OUTSIDE_THRESHOLD
592    }
593    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
594    #[inline(always)]
595    pub fn is_crossing_threshold(&self) -> bool {
596        **self == ADCMPINTEN3_A::CROSSING_THRESHOLD
597    }
598}
599impl core::ops::Deref for ADCMPINTEN3_R {
600    type Target = crate::FieldReader<u8, ADCMPINTEN3_A>;
601    #[inline(always)]
602    fn deref(&self) -> &Self::Target {
603        &self.0
604    }
605}
606#[doc = "Field `ADCMPINTEN3` writer - Channel 3 threshold comparison interrupt enable."]
607pub struct ADCMPINTEN3_W<'a> {
608    w: &'a mut W,
609}
610impl<'a> ADCMPINTEN3_W<'a> {
611    #[doc = r"Writes `variant` to the field"]
612    #[inline(always)]
613    pub fn variant(self, variant: ADCMPINTEN3_A) -> &'a mut W {
614        unsafe { self.bits(variant.into()) }
615    }
616    #[doc = "Disabled."]
617    #[inline(always)]
618    pub fn disabled(self) -> &'a mut W {
619        self.variant(ADCMPINTEN3_A::DISABLED)
620    }
621    #[doc = "Outside threshold."]
622    #[inline(always)]
623    pub fn outside_threshold(self) -> &'a mut W {
624        self.variant(ADCMPINTEN3_A::OUTSIDE_THRESHOLD)
625    }
626    #[doc = "Crossing threshold."]
627    #[inline(always)]
628    pub fn crossing_threshold(self) -> &'a mut W {
629        self.variant(ADCMPINTEN3_A::CROSSING_THRESHOLD)
630    }
631    #[doc = r"Writes raw bits to the field"]
632    #[inline(always)]
633    pub unsafe fn bits(self, value: u8) -> &'a mut W {
634        self.w.bits = (self.w.bits & !(0x03 << 9)) | ((value as u32 & 0x03) << 9);
635        self.w
636    }
637}
638#[doc = "Channel 4 threshold comparison interrupt enable.\n\nValue on reset: 0"]
639#[derive(Clone, Copy, Debug, PartialEq)]
640#[repr(u8)]
641pub enum ADCMPINTEN4_A {
642    #[doc = "0: Disabled."]
643    DISABLED = 0,
644    #[doc = "1: Outside threshold."]
645    OUTSIDE_THRESHOLD = 1,
646    #[doc = "2: Crossing threshold."]
647    CROSSING_THRESHOLD = 2,
648}
649impl From<ADCMPINTEN4_A> for u8 {
650    #[inline(always)]
651    fn from(variant: ADCMPINTEN4_A) -> Self {
652        variant as _
653    }
654}
655#[doc = "Field `ADCMPINTEN4` reader - Channel 4 threshold comparison interrupt enable."]
656pub struct ADCMPINTEN4_R(crate::FieldReader<u8, ADCMPINTEN4_A>);
657impl ADCMPINTEN4_R {
658    pub(crate) fn new(bits: u8) -> Self {
659        ADCMPINTEN4_R(crate::FieldReader::new(bits))
660    }
661    #[doc = r"Get enumerated values variant"]
662    #[inline(always)]
663    pub fn variant(&self) -> Option<ADCMPINTEN4_A> {
664        match self.bits {
665            0 => Some(ADCMPINTEN4_A::DISABLED),
666            1 => Some(ADCMPINTEN4_A::OUTSIDE_THRESHOLD),
667            2 => Some(ADCMPINTEN4_A::CROSSING_THRESHOLD),
668            _ => None,
669        }
670    }
671    #[doc = "Checks if the value of the field is `DISABLED`"]
672    #[inline(always)]
673    pub fn is_disabled(&self) -> bool {
674        **self == ADCMPINTEN4_A::DISABLED
675    }
676    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
677    #[inline(always)]
678    pub fn is_outside_threshold(&self) -> bool {
679        **self == ADCMPINTEN4_A::OUTSIDE_THRESHOLD
680    }
681    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
682    #[inline(always)]
683    pub fn is_crossing_threshold(&self) -> bool {
684        **self == ADCMPINTEN4_A::CROSSING_THRESHOLD
685    }
686}
687impl core::ops::Deref for ADCMPINTEN4_R {
688    type Target = crate::FieldReader<u8, ADCMPINTEN4_A>;
689    #[inline(always)]
690    fn deref(&self) -> &Self::Target {
691        &self.0
692    }
693}
694#[doc = "Field `ADCMPINTEN4` writer - Channel 4 threshold comparison interrupt enable."]
695pub struct ADCMPINTEN4_W<'a> {
696    w: &'a mut W,
697}
698impl<'a> ADCMPINTEN4_W<'a> {
699    #[doc = r"Writes `variant` to the field"]
700    #[inline(always)]
701    pub fn variant(self, variant: ADCMPINTEN4_A) -> &'a mut W {
702        unsafe { self.bits(variant.into()) }
703    }
704    #[doc = "Disabled."]
705    #[inline(always)]
706    pub fn disabled(self) -> &'a mut W {
707        self.variant(ADCMPINTEN4_A::DISABLED)
708    }
709    #[doc = "Outside threshold."]
710    #[inline(always)]
711    pub fn outside_threshold(self) -> &'a mut W {
712        self.variant(ADCMPINTEN4_A::OUTSIDE_THRESHOLD)
713    }
714    #[doc = "Crossing threshold."]
715    #[inline(always)]
716    pub fn crossing_threshold(self) -> &'a mut W {
717        self.variant(ADCMPINTEN4_A::CROSSING_THRESHOLD)
718    }
719    #[doc = r"Writes raw bits to the field"]
720    #[inline(always)]
721    pub unsafe fn bits(self, value: u8) -> &'a mut W {
722        self.w.bits = (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11);
723        self.w
724    }
725}
726#[doc = "Channel 5 threshold comparison interrupt enable.\n\nValue on reset: 0"]
727#[derive(Clone, Copy, Debug, PartialEq)]
728#[repr(u8)]
729pub enum ADCMPINTEN5_A {
730    #[doc = "0: Disabled."]
731    DISABLED = 0,
732    #[doc = "1: Outside threshold."]
733    OUTSIDE_THRESHOLD = 1,
734    #[doc = "2: Crossing threshold."]
735    CROSSING_THRESHOLD = 2,
736}
737impl From<ADCMPINTEN5_A> for u8 {
738    #[inline(always)]
739    fn from(variant: ADCMPINTEN5_A) -> Self {
740        variant as _
741    }
742}
743#[doc = "Field `ADCMPINTEN5` reader - Channel 5 threshold comparison interrupt enable."]
744pub struct ADCMPINTEN5_R(crate::FieldReader<u8, ADCMPINTEN5_A>);
745impl ADCMPINTEN5_R {
746    pub(crate) fn new(bits: u8) -> Self {
747        ADCMPINTEN5_R(crate::FieldReader::new(bits))
748    }
749    #[doc = r"Get enumerated values variant"]
750    #[inline(always)]
751    pub fn variant(&self) -> Option<ADCMPINTEN5_A> {
752        match self.bits {
753            0 => Some(ADCMPINTEN5_A::DISABLED),
754            1 => Some(ADCMPINTEN5_A::OUTSIDE_THRESHOLD),
755            2 => Some(ADCMPINTEN5_A::CROSSING_THRESHOLD),
756            _ => None,
757        }
758    }
759    #[doc = "Checks if the value of the field is `DISABLED`"]
760    #[inline(always)]
761    pub fn is_disabled(&self) -> bool {
762        **self == ADCMPINTEN5_A::DISABLED
763    }
764    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
765    #[inline(always)]
766    pub fn is_outside_threshold(&self) -> bool {
767        **self == ADCMPINTEN5_A::OUTSIDE_THRESHOLD
768    }
769    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
770    #[inline(always)]
771    pub fn is_crossing_threshold(&self) -> bool {
772        **self == ADCMPINTEN5_A::CROSSING_THRESHOLD
773    }
774}
775impl core::ops::Deref for ADCMPINTEN5_R {
776    type Target = crate::FieldReader<u8, ADCMPINTEN5_A>;
777    #[inline(always)]
778    fn deref(&self) -> &Self::Target {
779        &self.0
780    }
781}
782#[doc = "Field `ADCMPINTEN5` writer - Channel 5 threshold comparison interrupt enable."]
783pub struct ADCMPINTEN5_W<'a> {
784    w: &'a mut W,
785}
786impl<'a> ADCMPINTEN5_W<'a> {
787    #[doc = r"Writes `variant` to the field"]
788    #[inline(always)]
789    pub fn variant(self, variant: ADCMPINTEN5_A) -> &'a mut W {
790        unsafe { self.bits(variant.into()) }
791    }
792    #[doc = "Disabled."]
793    #[inline(always)]
794    pub fn disabled(self) -> &'a mut W {
795        self.variant(ADCMPINTEN5_A::DISABLED)
796    }
797    #[doc = "Outside threshold."]
798    #[inline(always)]
799    pub fn outside_threshold(self) -> &'a mut W {
800        self.variant(ADCMPINTEN5_A::OUTSIDE_THRESHOLD)
801    }
802    #[doc = "Crossing threshold."]
803    #[inline(always)]
804    pub fn crossing_threshold(self) -> &'a mut W {
805        self.variant(ADCMPINTEN5_A::CROSSING_THRESHOLD)
806    }
807    #[doc = r"Writes raw bits to the field"]
808    #[inline(always)]
809    pub unsafe fn bits(self, value: u8) -> &'a mut W {
810        self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13);
811        self.w
812    }
813}
814#[doc = "Channel 6 threshold comparison interrupt enable.\n\nValue on reset: 0"]
815#[derive(Clone, Copy, Debug, PartialEq)]
816#[repr(u8)]
817pub enum ADCMPINTEN6_A {
818    #[doc = "0: Disabled."]
819    DISABLED = 0,
820    #[doc = "1: Outside threshold."]
821    OUTSIDE_THRESHOLD = 1,
822    #[doc = "2: Crossing threshold."]
823    CROSSING_THRESHOLD = 2,
824}
825impl From<ADCMPINTEN6_A> for u8 {
826    #[inline(always)]
827    fn from(variant: ADCMPINTEN6_A) -> Self {
828        variant as _
829    }
830}
831#[doc = "Field `ADCMPINTEN6` reader - Channel 6 threshold comparison interrupt enable."]
832pub struct ADCMPINTEN6_R(crate::FieldReader<u8, ADCMPINTEN6_A>);
833impl ADCMPINTEN6_R {
834    pub(crate) fn new(bits: u8) -> Self {
835        ADCMPINTEN6_R(crate::FieldReader::new(bits))
836    }
837    #[doc = r"Get enumerated values variant"]
838    #[inline(always)]
839    pub fn variant(&self) -> Option<ADCMPINTEN6_A> {
840        match self.bits {
841            0 => Some(ADCMPINTEN6_A::DISABLED),
842            1 => Some(ADCMPINTEN6_A::OUTSIDE_THRESHOLD),
843            2 => Some(ADCMPINTEN6_A::CROSSING_THRESHOLD),
844            _ => None,
845        }
846    }
847    #[doc = "Checks if the value of the field is `DISABLED`"]
848    #[inline(always)]
849    pub fn is_disabled(&self) -> bool {
850        **self == ADCMPINTEN6_A::DISABLED
851    }
852    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
853    #[inline(always)]
854    pub fn is_outside_threshold(&self) -> bool {
855        **self == ADCMPINTEN6_A::OUTSIDE_THRESHOLD
856    }
857    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
858    #[inline(always)]
859    pub fn is_crossing_threshold(&self) -> bool {
860        **self == ADCMPINTEN6_A::CROSSING_THRESHOLD
861    }
862}
863impl core::ops::Deref for ADCMPINTEN6_R {
864    type Target = crate::FieldReader<u8, ADCMPINTEN6_A>;
865    #[inline(always)]
866    fn deref(&self) -> &Self::Target {
867        &self.0
868    }
869}
870#[doc = "Field `ADCMPINTEN6` writer - Channel 6 threshold comparison interrupt enable."]
871pub struct ADCMPINTEN6_W<'a> {
872    w: &'a mut W,
873}
874impl<'a> ADCMPINTEN6_W<'a> {
875    #[doc = r"Writes `variant` to the field"]
876    #[inline(always)]
877    pub fn variant(self, variant: ADCMPINTEN6_A) -> &'a mut W {
878        unsafe { self.bits(variant.into()) }
879    }
880    #[doc = "Disabled."]
881    #[inline(always)]
882    pub fn disabled(self) -> &'a mut W {
883        self.variant(ADCMPINTEN6_A::DISABLED)
884    }
885    #[doc = "Outside threshold."]
886    #[inline(always)]
887    pub fn outside_threshold(self) -> &'a mut W {
888        self.variant(ADCMPINTEN6_A::OUTSIDE_THRESHOLD)
889    }
890    #[doc = "Crossing threshold."]
891    #[inline(always)]
892    pub fn crossing_threshold(self) -> &'a mut W {
893        self.variant(ADCMPINTEN6_A::CROSSING_THRESHOLD)
894    }
895    #[doc = r"Writes raw bits to the field"]
896    #[inline(always)]
897    pub unsafe fn bits(self, value: u8) -> &'a mut W {
898        self.w.bits = (self.w.bits & !(0x03 << 15)) | ((value as u32 & 0x03) << 15);
899        self.w
900    }
901}
902#[doc = "Channel 7 threshold comparison interrupt enable.\n\nValue on reset: 0"]
903#[derive(Clone, Copy, Debug, PartialEq)]
904#[repr(u8)]
905pub enum ADCMPINTEN7_A {
906    #[doc = "0: Disabled."]
907    DISABLED = 0,
908    #[doc = "1: Outside threshold."]
909    OUTSIDE_THRESHOLD = 1,
910    #[doc = "2: Crossing threshold."]
911    CROSSING_THRESHOLD = 2,
912}
913impl From<ADCMPINTEN7_A> for u8 {
914    #[inline(always)]
915    fn from(variant: ADCMPINTEN7_A) -> Self {
916        variant as _
917    }
918}
919#[doc = "Field `ADCMPINTEN7` reader - Channel 7 threshold comparison interrupt enable."]
920pub struct ADCMPINTEN7_R(crate::FieldReader<u8, ADCMPINTEN7_A>);
921impl ADCMPINTEN7_R {
922    pub(crate) fn new(bits: u8) -> Self {
923        ADCMPINTEN7_R(crate::FieldReader::new(bits))
924    }
925    #[doc = r"Get enumerated values variant"]
926    #[inline(always)]
927    pub fn variant(&self) -> Option<ADCMPINTEN7_A> {
928        match self.bits {
929            0 => Some(ADCMPINTEN7_A::DISABLED),
930            1 => Some(ADCMPINTEN7_A::OUTSIDE_THRESHOLD),
931            2 => Some(ADCMPINTEN7_A::CROSSING_THRESHOLD),
932            _ => None,
933        }
934    }
935    #[doc = "Checks if the value of the field is `DISABLED`"]
936    #[inline(always)]
937    pub fn is_disabled(&self) -> bool {
938        **self == ADCMPINTEN7_A::DISABLED
939    }
940    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
941    #[inline(always)]
942    pub fn is_outside_threshold(&self) -> bool {
943        **self == ADCMPINTEN7_A::OUTSIDE_THRESHOLD
944    }
945    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
946    #[inline(always)]
947    pub fn is_crossing_threshold(&self) -> bool {
948        **self == ADCMPINTEN7_A::CROSSING_THRESHOLD
949    }
950}
951impl core::ops::Deref for ADCMPINTEN7_R {
952    type Target = crate::FieldReader<u8, ADCMPINTEN7_A>;
953    #[inline(always)]
954    fn deref(&self) -> &Self::Target {
955        &self.0
956    }
957}
958#[doc = "Field `ADCMPINTEN7` writer - Channel 7 threshold comparison interrupt enable."]
959pub struct ADCMPINTEN7_W<'a> {
960    w: &'a mut W,
961}
962impl<'a> ADCMPINTEN7_W<'a> {
963    #[doc = r"Writes `variant` to the field"]
964    #[inline(always)]
965    pub fn variant(self, variant: ADCMPINTEN7_A) -> &'a mut W {
966        unsafe { self.bits(variant.into()) }
967    }
968    #[doc = "Disabled."]
969    #[inline(always)]
970    pub fn disabled(self) -> &'a mut W {
971        self.variant(ADCMPINTEN7_A::DISABLED)
972    }
973    #[doc = "Outside threshold."]
974    #[inline(always)]
975    pub fn outside_threshold(self) -> &'a mut W {
976        self.variant(ADCMPINTEN7_A::OUTSIDE_THRESHOLD)
977    }
978    #[doc = "Crossing threshold."]
979    #[inline(always)]
980    pub fn crossing_threshold(self) -> &'a mut W {
981        self.variant(ADCMPINTEN7_A::CROSSING_THRESHOLD)
982    }
983    #[doc = r"Writes raw bits to the field"]
984    #[inline(always)]
985    pub unsafe fn bits(self, value: u8) -> &'a mut W {
986        self.w.bits = (self.w.bits & !(0x03 << 17)) | ((value as u32 & 0x03) << 17);
987        self.w
988    }
989}
990#[doc = "Channel 8 threshold comparison interrupt enable.\n\nValue on reset: 0"]
991#[derive(Clone, Copy, Debug, PartialEq)]
992#[repr(u8)]
993pub enum ADCMPINTEN8_A {
994    #[doc = "0: Disabled."]
995    DISABLED = 0,
996    #[doc = "1: Outside threshold."]
997    OUTSIDE_THRESHOLD = 1,
998    #[doc = "2: Crossing threshold."]
999    CROSSING_THRESHOLD = 2,
1000}
1001impl From<ADCMPINTEN8_A> for u8 {
1002    #[inline(always)]
1003    fn from(variant: ADCMPINTEN8_A) -> Self {
1004        variant as _
1005    }
1006}
1007#[doc = "Field `ADCMPINTEN8` reader - Channel 8 threshold comparison interrupt enable."]
1008pub struct ADCMPINTEN8_R(crate::FieldReader<u8, ADCMPINTEN8_A>);
1009impl ADCMPINTEN8_R {
1010    pub(crate) fn new(bits: u8) -> Self {
1011        ADCMPINTEN8_R(crate::FieldReader::new(bits))
1012    }
1013    #[doc = r"Get enumerated values variant"]
1014    #[inline(always)]
1015    pub fn variant(&self) -> Option<ADCMPINTEN8_A> {
1016        match self.bits {
1017            0 => Some(ADCMPINTEN8_A::DISABLED),
1018            1 => Some(ADCMPINTEN8_A::OUTSIDE_THRESHOLD),
1019            2 => Some(ADCMPINTEN8_A::CROSSING_THRESHOLD),
1020            _ => None,
1021        }
1022    }
1023    #[doc = "Checks if the value of the field is `DISABLED`"]
1024    #[inline(always)]
1025    pub fn is_disabled(&self) -> bool {
1026        **self == ADCMPINTEN8_A::DISABLED
1027    }
1028    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
1029    #[inline(always)]
1030    pub fn is_outside_threshold(&self) -> bool {
1031        **self == ADCMPINTEN8_A::OUTSIDE_THRESHOLD
1032    }
1033    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
1034    #[inline(always)]
1035    pub fn is_crossing_threshold(&self) -> bool {
1036        **self == ADCMPINTEN8_A::CROSSING_THRESHOLD
1037    }
1038}
1039impl core::ops::Deref for ADCMPINTEN8_R {
1040    type Target = crate::FieldReader<u8, ADCMPINTEN8_A>;
1041    #[inline(always)]
1042    fn deref(&self) -> &Self::Target {
1043        &self.0
1044    }
1045}
1046#[doc = "Field `ADCMPINTEN8` writer - Channel 8 threshold comparison interrupt enable."]
1047pub struct ADCMPINTEN8_W<'a> {
1048    w: &'a mut W,
1049}
1050impl<'a> ADCMPINTEN8_W<'a> {
1051    #[doc = r"Writes `variant` to the field"]
1052    #[inline(always)]
1053    pub fn variant(self, variant: ADCMPINTEN8_A) -> &'a mut W {
1054        unsafe { self.bits(variant.into()) }
1055    }
1056    #[doc = "Disabled."]
1057    #[inline(always)]
1058    pub fn disabled(self) -> &'a mut W {
1059        self.variant(ADCMPINTEN8_A::DISABLED)
1060    }
1061    #[doc = "Outside threshold."]
1062    #[inline(always)]
1063    pub fn outside_threshold(self) -> &'a mut W {
1064        self.variant(ADCMPINTEN8_A::OUTSIDE_THRESHOLD)
1065    }
1066    #[doc = "Crossing threshold."]
1067    #[inline(always)]
1068    pub fn crossing_threshold(self) -> &'a mut W {
1069        self.variant(ADCMPINTEN8_A::CROSSING_THRESHOLD)
1070    }
1071    #[doc = r"Writes raw bits to the field"]
1072    #[inline(always)]
1073    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1074        self.w.bits = (self.w.bits & !(0x03 << 19)) | ((value as u32 & 0x03) << 19);
1075        self.w
1076    }
1077}
1078#[doc = "Channel 9 threshold comparison interrupt enable.\n\nValue on reset: 0"]
1079#[derive(Clone, Copy, Debug, PartialEq)]
1080#[repr(u8)]
1081pub enum ADCMPINTEN9_A {
1082    #[doc = "0: Disabled."]
1083    DISABLED = 0,
1084    #[doc = "1: Outside threshold."]
1085    OUTSIDE_THRESHOLD = 1,
1086    #[doc = "2: Crossing threshold."]
1087    CROSSING_THRESHOLD = 2,
1088}
1089impl From<ADCMPINTEN9_A> for u8 {
1090    #[inline(always)]
1091    fn from(variant: ADCMPINTEN9_A) -> Self {
1092        variant as _
1093    }
1094}
1095#[doc = "Field `ADCMPINTEN9` reader - Channel 9 threshold comparison interrupt enable."]
1096pub struct ADCMPINTEN9_R(crate::FieldReader<u8, ADCMPINTEN9_A>);
1097impl ADCMPINTEN9_R {
1098    pub(crate) fn new(bits: u8) -> Self {
1099        ADCMPINTEN9_R(crate::FieldReader::new(bits))
1100    }
1101    #[doc = r"Get enumerated values variant"]
1102    #[inline(always)]
1103    pub fn variant(&self) -> Option<ADCMPINTEN9_A> {
1104        match self.bits {
1105            0 => Some(ADCMPINTEN9_A::DISABLED),
1106            1 => Some(ADCMPINTEN9_A::OUTSIDE_THRESHOLD),
1107            2 => Some(ADCMPINTEN9_A::CROSSING_THRESHOLD),
1108            _ => None,
1109        }
1110    }
1111    #[doc = "Checks if the value of the field is `DISABLED`"]
1112    #[inline(always)]
1113    pub fn is_disabled(&self) -> bool {
1114        **self == ADCMPINTEN9_A::DISABLED
1115    }
1116    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
1117    #[inline(always)]
1118    pub fn is_outside_threshold(&self) -> bool {
1119        **self == ADCMPINTEN9_A::OUTSIDE_THRESHOLD
1120    }
1121    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
1122    #[inline(always)]
1123    pub fn is_crossing_threshold(&self) -> bool {
1124        **self == ADCMPINTEN9_A::CROSSING_THRESHOLD
1125    }
1126}
1127impl core::ops::Deref for ADCMPINTEN9_R {
1128    type Target = crate::FieldReader<u8, ADCMPINTEN9_A>;
1129    #[inline(always)]
1130    fn deref(&self) -> &Self::Target {
1131        &self.0
1132    }
1133}
1134#[doc = "Field `ADCMPINTEN9` writer - Channel 9 threshold comparison interrupt enable."]
1135pub struct ADCMPINTEN9_W<'a> {
1136    w: &'a mut W,
1137}
1138impl<'a> ADCMPINTEN9_W<'a> {
1139    #[doc = r"Writes `variant` to the field"]
1140    #[inline(always)]
1141    pub fn variant(self, variant: ADCMPINTEN9_A) -> &'a mut W {
1142        unsafe { self.bits(variant.into()) }
1143    }
1144    #[doc = "Disabled."]
1145    #[inline(always)]
1146    pub fn disabled(self) -> &'a mut W {
1147        self.variant(ADCMPINTEN9_A::DISABLED)
1148    }
1149    #[doc = "Outside threshold."]
1150    #[inline(always)]
1151    pub fn outside_threshold(self) -> &'a mut W {
1152        self.variant(ADCMPINTEN9_A::OUTSIDE_THRESHOLD)
1153    }
1154    #[doc = "Crossing threshold."]
1155    #[inline(always)]
1156    pub fn crossing_threshold(self) -> &'a mut W {
1157        self.variant(ADCMPINTEN9_A::CROSSING_THRESHOLD)
1158    }
1159    #[doc = r"Writes raw bits to the field"]
1160    #[inline(always)]
1161    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1162        self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21);
1163        self.w
1164    }
1165}
1166#[doc = "Channel 10 threshold comparison interrupt enable.\n\nValue on reset: 0"]
1167#[derive(Clone, Copy, Debug, PartialEq)]
1168#[repr(u8)]
1169pub enum ADCMPINTEN10_A {
1170    #[doc = "0: Disabled."]
1171    DISABLED = 0,
1172    #[doc = "1: Outside threshold."]
1173    OUTSIDE_THRESHOLD = 1,
1174    #[doc = "2: Crossing threshold."]
1175    CROSSING_THRESHOLD = 2,
1176}
1177impl From<ADCMPINTEN10_A> for u8 {
1178    #[inline(always)]
1179    fn from(variant: ADCMPINTEN10_A) -> Self {
1180        variant as _
1181    }
1182}
1183#[doc = "Field `ADCMPINTEN10` reader - Channel 10 threshold comparison interrupt enable."]
1184pub struct ADCMPINTEN10_R(crate::FieldReader<u8, ADCMPINTEN10_A>);
1185impl ADCMPINTEN10_R {
1186    pub(crate) fn new(bits: u8) -> Self {
1187        ADCMPINTEN10_R(crate::FieldReader::new(bits))
1188    }
1189    #[doc = r"Get enumerated values variant"]
1190    #[inline(always)]
1191    pub fn variant(&self) -> Option<ADCMPINTEN10_A> {
1192        match self.bits {
1193            0 => Some(ADCMPINTEN10_A::DISABLED),
1194            1 => Some(ADCMPINTEN10_A::OUTSIDE_THRESHOLD),
1195            2 => Some(ADCMPINTEN10_A::CROSSING_THRESHOLD),
1196            _ => None,
1197        }
1198    }
1199    #[doc = "Checks if the value of the field is `DISABLED`"]
1200    #[inline(always)]
1201    pub fn is_disabled(&self) -> bool {
1202        **self == ADCMPINTEN10_A::DISABLED
1203    }
1204    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
1205    #[inline(always)]
1206    pub fn is_outside_threshold(&self) -> bool {
1207        **self == ADCMPINTEN10_A::OUTSIDE_THRESHOLD
1208    }
1209    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
1210    #[inline(always)]
1211    pub fn is_crossing_threshold(&self) -> bool {
1212        **self == ADCMPINTEN10_A::CROSSING_THRESHOLD
1213    }
1214}
1215impl core::ops::Deref for ADCMPINTEN10_R {
1216    type Target = crate::FieldReader<u8, ADCMPINTEN10_A>;
1217    #[inline(always)]
1218    fn deref(&self) -> &Self::Target {
1219        &self.0
1220    }
1221}
1222#[doc = "Field `ADCMPINTEN10` writer - Channel 10 threshold comparison interrupt enable."]
1223pub struct ADCMPINTEN10_W<'a> {
1224    w: &'a mut W,
1225}
1226impl<'a> ADCMPINTEN10_W<'a> {
1227    #[doc = r"Writes `variant` to the field"]
1228    #[inline(always)]
1229    pub fn variant(self, variant: ADCMPINTEN10_A) -> &'a mut W {
1230        unsafe { self.bits(variant.into()) }
1231    }
1232    #[doc = "Disabled."]
1233    #[inline(always)]
1234    pub fn disabled(self) -> &'a mut W {
1235        self.variant(ADCMPINTEN10_A::DISABLED)
1236    }
1237    #[doc = "Outside threshold."]
1238    #[inline(always)]
1239    pub fn outside_threshold(self) -> &'a mut W {
1240        self.variant(ADCMPINTEN10_A::OUTSIDE_THRESHOLD)
1241    }
1242    #[doc = "Crossing threshold."]
1243    #[inline(always)]
1244    pub fn crossing_threshold(self) -> &'a mut W {
1245        self.variant(ADCMPINTEN10_A::CROSSING_THRESHOLD)
1246    }
1247    #[doc = r"Writes raw bits to the field"]
1248    #[inline(always)]
1249    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1250        self.w.bits = (self.w.bits & !(0x03 << 23)) | ((value as u32 & 0x03) << 23);
1251        self.w
1252    }
1253}
1254#[doc = "Channel 11 threshold comparison interrupt enable.\n\nValue on reset: 0"]
1255#[derive(Clone, Copy, Debug, PartialEq)]
1256#[repr(u8)]
1257pub enum ADCMPINTEN11_A {
1258    #[doc = "0: Disabled."]
1259    DISABLED = 0,
1260    #[doc = "1: Outside threshold."]
1261    OUTSIDE_THRESHOLD = 1,
1262    #[doc = "2: Crossing threshold."]
1263    CROSSING_THRESHOLD = 2,
1264}
1265impl From<ADCMPINTEN11_A> for u8 {
1266    #[inline(always)]
1267    fn from(variant: ADCMPINTEN11_A) -> Self {
1268        variant as _
1269    }
1270}
1271#[doc = "Field `ADCMPINTEN11` reader - Channel 11 threshold comparison interrupt enable."]
1272pub struct ADCMPINTEN11_R(crate::FieldReader<u8, ADCMPINTEN11_A>);
1273impl ADCMPINTEN11_R {
1274    pub(crate) fn new(bits: u8) -> Self {
1275        ADCMPINTEN11_R(crate::FieldReader::new(bits))
1276    }
1277    #[doc = r"Get enumerated values variant"]
1278    #[inline(always)]
1279    pub fn variant(&self) -> Option<ADCMPINTEN11_A> {
1280        match self.bits {
1281            0 => Some(ADCMPINTEN11_A::DISABLED),
1282            1 => Some(ADCMPINTEN11_A::OUTSIDE_THRESHOLD),
1283            2 => Some(ADCMPINTEN11_A::CROSSING_THRESHOLD),
1284            _ => None,
1285        }
1286    }
1287    #[doc = "Checks if the value of the field is `DISABLED`"]
1288    #[inline(always)]
1289    pub fn is_disabled(&self) -> bool {
1290        **self == ADCMPINTEN11_A::DISABLED
1291    }
1292    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
1293    #[inline(always)]
1294    pub fn is_outside_threshold(&self) -> bool {
1295        **self == ADCMPINTEN11_A::OUTSIDE_THRESHOLD
1296    }
1297    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
1298    #[inline(always)]
1299    pub fn is_crossing_threshold(&self) -> bool {
1300        **self == ADCMPINTEN11_A::CROSSING_THRESHOLD
1301    }
1302}
1303impl core::ops::Deref for ADCMPINTEN11_R {
1304    type Target = crate::FieldReader<u8, ADCMPINTEN11_A>;
1305    #[inline(always)]
1306    fn deref(&self) -> &Self::Target {
1307        &self.0
1308    }
1309}
1310#[doc = "Field `ADCMPINTEN11` writer - Channel 11 threshold comparison interrupt enable."]
1311pub struct ADCMPINTEN11_W<'a> {
1312    w: &'a mut W,
1313}
1314impl<'a> ADCMPINTEN11_W<'a> {
1315    #[doc = r"Writes `variant` to the field"]
1316    #[inline(always)]
1317    pub fn variant(self, variant: ADCMPINTEN11_A) -> &'a mut W {
1318        unsafe { self.bits(variant.into()) }
1319    }
1320    #[doc = "Disabled."]
1321    #[inline(always)]
1322    pub fn disabled(self) -> &'a mut W {
1323        self.variant(ADCMPINTEN11_A::DISABLED)
1324    }
1325    #[doc = "Outside threshold."]
1326    #[inline(always)]
1327    pub fn outside_threshold(self) -> &'a mut W {
1328        self.variant(ADCMPINTEN11_A::OUTSIDE_THRESHOLD)
1329    }
1330    #[doc = "Crossing threshold."]
1331    #[inline(always)]
1332    pub fn crossing_threshold(self) -> &'a mut W {
1333        self.variant(ADCMPINTEN11_A::CROSSING_THRESHOLD)
1334    }
1335    #[doc = r"Writes raw bits to the field"]
1336    #[inline(always)]
1337    pub unsafe fn bits(self, value: u8) -> &'a mut W {
1338        self.w.bits = (self.w.bits & !(0x03 << 25)) | ((value as u32 & 0x03) << 25);
1339        self.w
1340    }
1341}
1342impl R {
1343    #[doc = "Bit 0 - Sequence A interrupt enable."]
1344    #[inline(always)]
1345    pub fn seqa_inten(&self) -> SEQA_INTEN_R {
1346        SEQA_INTEN_R::new((self.bits & 0x01) != 0)
1347    }
1348    #[doc = "Bit 1 - Sequence B interrupt enable."]
1349    #[inline(always)]
1350    pub fn seqb_inten(&self) -> SEQB_INTEN_R {
1351        SEQB_INTEN_R::new(((self.bits >> 1) & 0x01) != 0)
1352    }
1353    #[doc = "Bit 2 - Overrun interrupt enable."]
1354    #[inline(always)]
1355    pub fn ovr_inten(&self) -> OVR_INTEN_R {
1356        OVR_INTEN_R::new(((self.bits >> 2) & 0x01) != 0)
1357    }
1358    #[doc = "Bits 3:4 - Threshold comparison interrupt enable for channel 0."]
1359    #[inline(always)]
1360    pub fn adcmpinten0(&self) -> ADCMPINTEN0_R {
1361        ADCMPINTEN0_R::new(((self.bits >> 3) & 0x03) as u8)
1362    }
1363    #[doc = "Bits 5:6 - Channel 1 threshold comparison interrupt enable."]
1364    #[inline(always)]
1365    pub fn adcmpinten1(&self) -> ADCMPINTEN1_R {
1366        ADCMPINTEN1_R::new(((self.bits >> 5) & 0x03) as u8)
1367    }
1368    #[doc = "Bits 7:8 - Channel 2 threshold comparison interrupt enable."]
1369    #[inline(always)]
1370    pub fn adcmpinten2(&self) -> ADCMPINTEN2_R {
1371        ADCMPINTEN2_R::new(((self.bits >> 7) & 0x03) as u8)
1372    }
1373    #[doc = "Bits 9:10 - Channel 3 threshold comparison interrupt enable."]
1374    #[inline(always)]
1375    pub fn adcmpinten3(&self) -> ADCMPINTEN3_R {
1376        ADCMPINTEN3_R::new(((self.bits >> 9) & 0x03) as u8)
1377    }
1378    #[doc = "Bits 11:12 - Channel 4 threshold comparison interrupt enable."]
1379    #[inline(always)]
1380    pub fn adcmpinten4(&self) -> ADCMPINTEN4_R {
1381        ADCMPINTEN4_R::new(((self.bits >> 11) & 0x03) as u8)
1382    }
1383    #[doc = "Bits 13:14 - Channel 5 threshold comparison interrupt enable."]
1384    #[inline(always)]
1385    pub fn adcmpinten5(&self) -> ADCMPINTEN5_R {
1386        ADCMPINTEN5_R::new(((self.bits >> 13) & 0x03) as u8)
1387    }
1388    #[doc = "Bits 15:16 - Channel 6 threshold comparison interrupt enable."]
1389    #[inline(always)]
1390    pub fn adcmpinten6(&self) -> ADCMPINTEN6_R {
1391        ADCMPINTEN6_R::new(((self.bits >> 15) & 0x03) as u8)
1392    }
1393    #[doc = "Bits 17:18 - Channel 7 threshold comparison interrupt enable."]
1394    #[inline(always)]
1395    pub fn adcmpinten7(&self) -> ADCMPINTEN7_R {
1396        ADCMPINTEN7_R::new(((self.bits >> 17) & 0x03) as u8)
1397    }
1398    #[doc = "Bits 19:20 - Channel 8 threshold comparison interrupt enable."]
1399    #[inline(always)]
1400    pub fn adcmpinten8(&self) -> ADCMPINTEN8_R {
1401        ADCMPINTEN8_R::new(((self.bits >> 19) & 0x03) as u8)
1402    }
1403    #[doc = "Bits 21:22 - Channel 9 threshold comparison interrupt enable."]
1404    #[inline(always)]
1405    pub fn adcmpinten9(&self) -> ADCMPINTEN9_R {
1406        ADCMPINTEN9_R::new(((self.bits >> 21) & 0x03) as u8)
1407    }
1408    #[doc = "Bits 23:24 - Channel 10 threshold comparison interrupt enable."]
1409    #[inline(always)]
1410    pub fn adcmpinten10(&self) -> ADCMPINTEN10_R {
1411        ADCMPINTEN10_R::new(((self.bits >> 23) & 0x03) as u8)
1412    }
1413    #[doc = "Bits 25:26 - Channel 11 threshold comparison interrupt enable."]
1414    #[inline(always)]
1415    pub fn adcmpinten11(&self) -> ADCMPINTEN11_R {
1416        ADCMPINTEN11_R::new(((self.bits >> 25) & 0x03) as u8)
1417    }
1418}
1419impl W {
1420    #[doc = "Bit 0 - Sequence A interrupt enable."]
1421    #[inline(always)]
1422    pub fn seqa_inten(&mut self) -> SEQA_INTEN_W {
1423        SEQA_INTEN_W { w: self }
1424    }
1425    #[doc = "Bit 1 - Sequence B interrupt enable."]
1426    #[inline(always)]
1427    pub fn seqb_inten(&mut self) -> SEQB_INTEN_W {
1428        SEQB_INTEN_W { w: self }
1429    }
1430    #[doc = "Bit 2 - Overrun interrupt enable."]
1431    #[inline(always)]
1432    pub fn ovr_inten(&mut self) -> OVR_INTEN_W {
1433        OVR_INTEN_W { w: self }
1434    }
1435    #[doc = "Bits 3:4 - Threshold comparison interrupt enable for channel 0."]
1436    #[inline(always)]
1437    pub fn adcmpinten0(&mut self) -> ADCMPINTEN0_W {
1438        ADCMPINTEN0_W { w: self }
1439    }
1440    #[doc = "Bits 5:6 - Channel 1 threshold comparison interrupt enable."]
1441    #[inline(always)]
1442    pub fn adcmpinten1(&mut self) -> ADCMPINTEN1_W {
1443        ADCMPINTEN1_W { w: self }
1444    }
1445    #[doc = "Bits 7:8 - Channel 2 threshold comparison interrupt enable."]
1446    #[inline(always)]
1447    pub fn adcmpinten2(&mut self) -> ADCMPINTEN2_W {
1448        ADCMPINTEN2_W { w: self }
1449    }
1450    #[doc = "Bits 9:10 - Channel 3 threshold comparison interrupt enable."]
1451    #[inline(always)]
1452    pub fn adcmpinten3(&mut self) -> ADCMPINTEN3_W {
1453        ADCMPINTEN3_W { w: self }
1454    }
1455    #[doc = "Bits 11:12 - Channel 4 threshold comparison interrupt enable."]
1456    #[inline(always)]
1457    pub fn adcmpinten4(&mut self) -> ADCMPINTEN4_W {
1458        ADCMPINTEN4_W { w: self }
1459    }
1460    #[doc = "Bits 13:14 - Channel 5 threshold comparison interrupt enable."]
1461    #[inline(always)]
1462    pub fn adcmpinten5(&mut self) -> ADCMPINTEN5_W {
1463        ADCMPINTEN5_W { w: self }
1464    }
1465    #[doc = "Bits 15:16 - Channel 6 threshold comparison interrupt enable."]
1466    #[inline(always)]
1467    pub fn adcmpinten6(&mut self) -> ADCMPINTEN6_W {
1468        ADCMPINTEN6_W { w: self }
1469    }
1470    #[doc = "Bits 17:18 - Channel 7 threshold comparison interrupt enable."]
1471    #[inline(always)]
1472    pub fn adcmpinten7(&mut self) -> ADCMPINTEN7_W {
1473        ADCMPINTEN7_W { w: self }
1474    }
1475    #[doc = "Bits 19:20 - Channel 8 threshold comparison interrupt enable."]
1476    #[inline(always)]
1477    pub fn adcmpinten8(&mut self) -> ADCMPINTEN8_W {
1478        ADCMPINTEN8_W { w: self }
1479    }
1480    #[doc = "Bits 21:22 - Channel 9 threshold comparison interrupt enable."]
1481    #[inline(always)]
1482    pub fn adcmpinten9(&mut self) -> ADCMPINTEN9_W {
1483        ADCMPINTEN9_W { w: self }
1484    }
1485    #[doc = "Bits 23:24 - Channel 10 threshold comparison interrupt enable."]
1486    #[inline(always)]
1487    pub fn adcmpinten10(&mut self) -> ADCMPINTEN10_W {
1488        ADCMPINTEN10_W { w: self }
1489    }
1490    #[doc = "Bits 25:26 - Channel 11 threshold comparison interrupt enable."]
1491    #[inline(always)]
1492    pub fn adcmpinten11(&mut self) -> ADCMPINTEN11_W {
1493        ADCMPINTEN11_W { w: self }
1494    }
1495    #[doc = "Writes raw bits to the register."]
1496    #[inline(always)]
1497    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1498        self.0.bits(bits);
1499        self
1500    }
1501}
1502#[doc = "ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
1503pub struct INTEN_SPEC;
1504impl crate::RegisterSpec for INTEN_SPEC {
1505    type Ux = u32;
1506}
1507#[doc = "`read()` method returns [inten::R](R) reader structure"]
1508impl crate::Readable for INTEN_SPEC {
1509    type Reader = R;
1510}
1511#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
1512impl crate::Writable for INTEN_SPEC {
1513    type Writer = W;
1514}
1515#[doc = "`reset()` method sets INTEN to value 0"]
1516impl crate::Resettable for INTEN_SPEC {
1517    #[inline(always)]
1518    fn reset_value() -> Self::Ux {
1519        0
1520    }
1521}
lpc82x_pac/adc0/inten.rs

lpc82x_pac/adc0/
inten.rs
