Struct lpc82x_hal::syscon::UARTFRG

pub struct UARTFRG<'syscon> { /* fields omitted */ }

UART Fractional Baud Rate Generator

Controls the common clock for all UART peripherals (U_PCLK).

Can also be used to control the UART FRG using various methods on syscon::Handle.

Methods

impl<'syscon> UARTFRG<'syscon>

pub fn set_clkdiv(&mut self, value: u8)

Set UART clock divider value (UARTCLKDIV)

See user manual, section 5.6.15.

pub fn set_frgmult(&mut self, value: u8)

Set UART fractional generator multiplier value (UARTFRGMULT)

See user manual, section 5.6.20.

pub fn set_frgdiv(&mut self, value: u8)

Set UART fractional generator divider value (UARTFRGDIV)

See user manual, section 5.6.19.

Trait Implementations

impl<'a> ResetControl for UARTFRG<'a>

fn assert_reset<'w>(&mut self, w: &'w mut W) -> &'w mut W

Internal method to assert peripheral reset

fn clear_reset<'w>(&mut self, w: &'w mut W) -> &'w mut W

Internal method to clear peripheral reset