lpc81x_pac/lpc811/syscon/
mainclkuen.rs

1#[doc = "Register `MAINCLKUEN` reader"]
2pub struct R(crate::R<MAINCLKUEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MAINCLKUEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MAINCLKUEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MAINCLKUEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MAINCLKUEN` writer"]
17pub struct W(crate::W<MAINCLKUEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MAINCLKUEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MAINCLKUEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MAINCLKUEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENA` reader - Enable main clock source update."]
38pub type ENA_R = crate::BitReader<ENA_A>;
39#[doc = "Enable main clock source update.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum ENA_A {
42    #[doc = "0: No change."]
43    ENA_0 = 0,
44    #[doc = "1: Update clock source."]
45    ENA_1 = 1,
46}
47impl From<ENA_A> for bool {
48    #[inline(always)]
49    fn from(variant: ENA_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl ENA_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> ENA_A {
57        match self.bits {
58            false => ENA_A::ENA_0,
59            true => ENA_A::ENA_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `ENA_0`"]
63    #[inline(always)]
64    pub fn is_ena_0(&self) -> bool {
65        *self == ENA_A::ENA_0
66    }
67    #[doc = "Checks if the value of the field is `ENA_1`"]
68    #[inline(always)]
69    pub fn is_ena_1(&self) -> bool {
70        *self == ENA_A::ENA_1
71    }
72}
73#[doc = "Field `ENA` writer - Enable main clock source update."]
74pub type ENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, MAINCLKUEN_SPEC, ENA_A, O>;
75impl<'a, const O: u8> ENA_W<'a, O> {
76    #[doc = "No change."]
77    #[inline(always)]
78    pub fn ena_0(self) -> &'a mut W {
79        self.variant(ENA_A::ENA_0)
80    }
81    #[doc = "Update clock source."]
82    #[inline(always)]
83    pub fn ena_1(self) -> &'a mut W {
84        self.variant(ENA_A::ENA_1)
85    }
86}
87impl R {
88    #[doc = "Bit 0 - Enable main clock source update."]
89    #[inline(always)]
90    pub fn ena(&self) -> ENA_R {
91        ENA_R::new((self.bits & 1) != 0)
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Enable main clock source update."]
96    #[inline(always)]
97    pub fn ena(&mut self) -> ENA_W<0> {
98        ENA_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Main clock source update enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclkuen](index.html) module"]
108pub struct MAINCLKUEN_SPEC;
109impl crate::RegisterSpec for MAINCLKUEN_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [mainclkuen::R](R) reader structure"]
113impl crate::Readable for MAINCLKUEN_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [mainclkuen::W](W) writer structure"]
117impl crate::Writable for MAINCLKUEN_SPEC {
118    type Writer = W;
119}
120#[doc = "`reset()` method sets MAINCLKUEN to value 0"]
121impl crate::Resettable for MAINCLKUEN_SPEC {
122    #[inline(always)]
123    fn reset_value() -> Self::Ux {
124        0
125    }
126}
lpc81x_pac/lpc811/syscon/mainclkuen.rs

lpc81x_pac/lpc811/syscon/
mainclkuen.rs
