lpc81x_pac/lpc810/usart0/
ctl.rs1#[doc = "Register `CTL` reader"]
2pub struct R(crate::R<CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTL` writer"]
17pub struct W(crate::W<CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXBRKEN` reader - Break Enable."]
38pub type TXBRKEN_R = crate::BitReader<TXBRKEN_A>;
39#[doc = "Break Enable.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum TXBRKEN_A {
42 #[doc = "0: Normal operation."]
43 NORMAL = 0,
44 #[doc = "1: Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN."]
45 CONTINOUS = 1,
46}
47impl From<TXBRKEN_A> for bool {
48 #[inline(always)]
49 fn from(variant: TXBRKEN_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl TXBRKEN_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> TXBRKEN_A {
57 match self.bits {
58 false => TXBRKEN_A::NORMAL,
59 true => TXBRKEN_A::CONTINOUS,
60 }
61 }
62 #[doc = "Checks if the value of the field is `NORMAL`"]
63 #[inline(always)]
64 pub fn is_normal(&self) -> bool {
65 *self == TXBRKEN_A::NORMAL
66 }
67 #[doc = "Checks if the value of the field is `CONTINOUS`"]
68 #[inline(always)]
69 pub fn is_continous(&self) -> bool {
70 *self == TXBRKEN_A::CONTINOUS
71 }
72}
73#[doc = "Field `TXBRKEN` writer - Break Enable."]
74pub type TXBRKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, TXBRKEN_A, O>;
75impl<'a, const O: u8> TXBRKEN_W<'a, O> {
76 #[doc = "Normal operation."]
77 #[inline(always)]
78 pub fn normal(self) -> &'a mut W {
79 self.variant(TXBRKEN_A::NORMAL)
80 }
81 #[doc = "Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN."]
82 #[inline(always)]
83 pub fn continous(self) -> &'a mut W {
84 self.variant(TXBRKEN_A::CONTINOUS)
85 }
86}
87#[doc = "Field `ADDRDET` reader - Enable address detect mode."]
88pub type ADDRDET_R = crate::BitReader<ADDRDET_A>;
89#[doc = "Enable address detect mode.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq)]
91pub enum ADDRDET_A {
92 #[doc = "0: Disabled. The USART presents all incoming data."]
93 DISABLED = 0,
94 #[doc = "1: Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally."]
95 ENABLED = 1,
96}
97impl From<ADDRDET_A> for bool {
98 #[inline(always)]
99 fn from(variant: ADDRDET_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl ADDRDET_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> ADDRDET_A {
107 match self.bits {
108 false => ADDRDET_A::DISABLED,
109 true => ADDRDET_A::ENABLED,
110 }
111 }
112 #[doc = "Checks if the value of the field is `DISABLED`"]
113 #[inline(always)]
114 pub fn is_disabled(&self) -> bool {
115 *self == ADDRDET_A::DISABLED
116 }
117 #[doc = "Checks if the value of the field is `ENABLED`"]
118 #[inline(always)]
119 pub fn is_enabled(&self) -> bool {
120 *self == ADDRDET_A::ENABLED
121 }
122}
123#[doc = "Field `ADDRDET` writer - Enable address detect mode."]
124pub type ADDRDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, ADDRDET_A, O>;
125impl<'a, const O: u8> ADDRDET_W<'a, O> {
126 #[doc = "Disabled. The USART presents all incoming data."]
127 #[inline(always)]
128 pub fn disabled(self) -> &'a mut W {
129 self.variant(ADDRDET_A::DISABLED)
130 }
131 #[doc = "Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally."]
132 #[inline(always)]
133 pub fn enabled(self) -> &'a mut W {
134 self.variant(ADDRDET_A::ENABLED)
135 }
136}
137#[doc = "Field `TXDIS` reader - Transmit Disable."]
138pub type TXDIS_R = crate::BitReader<TXDIS_A>;
139#[doc = "Transmit Disable.\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum TXDIS_A {
142 #[doc = "0: Not disabled. USART transmitter is not disabled."]
143 ENABLED = 0,
144 #[doc = "1: Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control."]
145 DISABLED = 1,
146}
147impl From<TXDIS_A> for bool {
148 #[inline(always)]
149 fn from(variant: TXDIS_A) -> Self {
150 variant as u8 != 0
151 }
152}
153impl TXDIS_R {
154 #[doc = "Get enumerated values variant"]
155 #[inline(always)]
156 pub fn variant(&self) -> TXDIS_A {
157 match self.bits {
158 false => TXDIS_A::ENABLED,
159 true => TXDIS_A::DISABLED,
160 }
161 }
162 #[doc = "Checks if the value of the field is `ENABLED`"]
163 #[inline(always)]
164 pub fn is_enabled(&self) -> bool {
165 *self == TXDIS_A::ENABLED
166 }
167 #[doc = "Checks if the value of the field is `DISABLED`"]
168 #[inline(always)]
169 pub fn is_disabled(&self) -> bool {
170 *self == TXDIS_A::DISABLED
171 }
172}
173#[doc = "Field `TXDIS` writer - Transmit Disable."]
174pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, TXDIS_A, O>;
175impl<'a, const O: u8> TXDIS_W<'a, O> {
176 #[doc = "Not disabled. USART transmitter is not disabled."]
177 #[inline(always)]
178 pub fn enabled(self) -> &'a mut W {
179 self.variant(TXDIS_A::ENABLED)
180 }
181 #[doc = "Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control."]
182 #[inline(always)]
183 pub fn disabled(self) -> &'a mut W {
184 self.variant(TXDIS_A::DISABLED)
185 }
186}
187#[doc = "Field `CC` reader - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."]
188pub type CC_R = crate::BitReader<CC_A>;
189#[doc = "Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq)]
191pub enum CC_A {
192 #[doc = "0: Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received."]
193 CLOCK_ON_CHARACTER = 0,
194 #[doc = "1: Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)."]
195 CONTINOUS_CLOCK = 1,
196}
197impl From<CC_A> for bool {
198 #[inline(always)]
199 fn from(variant: CC_A) -> Self {
200 variant as u8 != 0
201 }
202}
203impl CC_R {
204 #[doc = "Get enumerated values variant"]
205 #[inline(always)]
206 pub fn variant(&self) -> CC_A {
207 match self.bits {
208 false => CC_A::CLOCK_ON_CHARACTER,
209 true => CC_A::CONTINOUS_CLOCK,
210 }
211 }
212 #[doc = "Checks if the value of the field is `CLOCK_ON_CHARACTER`"]
213 #[inline(always)]
214 pub fn is_clock_on_character(&self) -> bool {
215 *self == CC_A::CLOCK_ON_CHARACTER
216 }
217 #[doc = "Checks if the value of the field is `CONTINOUS_CLOCK`"]
218 #[inline(always)]
219 pub fn is_continous_clock(&self) -> bool {
220 *self == CC_A::CONTINOUS_CLOCK
221 }
222}
223#[doc = "Field `CC` writer - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."]
224pub type CC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, CC_A, O>;
225impl<'a, const O: u8> CC_W<'a, O> {
226 #[doc = "Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received."]
227 #[inline(always)]
228 pub fn clock_on_character(self) -> &'a mut W {
229 self.variant(CC_A::CLOCK_ON_CHARACTER)
230 }
231 #[doc = "Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD)."]
232 #[inline(always)]
233 pub fn continous_clock(self) -> &'a mut W {
234 self.variant(CC_A::CONTINOUS_CLOCK)
235 }
236}
237#[doc = "Field `CLRCCONRX` reader - Clear Continuous Clock."]
238pub type CLRCCONRX_R = crate::BitReader<CLRCCONRX_A>;
239#[doc = "Clear Continuous Clock.\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq)]
241pub enum CLRCCONRX_A {
242 #[doc = "0: No effect. No effect on the CC bit."]
243 NO_EFFECT = 0,
244 #[doc = "1: Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time."]
245 AUTO_CLEAR = 1,
246}
247impl From<CLRCCONRX_A> for bool {
248 #[inline(always)]
249 fn from(variant: CLRCCONRX_A) -> Self {
250 variant as u8 != 0
251 }
252}
253impl CLRCCONRX_R {
254 #[doc = "Get enumerated values variant"]
255 #[inline(always)]
256 pub fn variant(&self) -> CLRCCONRX_A {
257 match self.bits {
258 false => CLRCCONRX_A::NO_EFFECT,
259 true => CLRCCONRX_A::AUTO_CLEAR,
260 }
261 }
262 #[doc = "Checks if the value of the field is `NO_EFFECT`"]
263 #[inline(always)]
264 pub fn is_no_effect(&self) -> bool {
265 *self == CLRCCONRX_A::NO_EFFECT
266 }
267 #[doc = "Checks if the value of the field is `AUTO_CLEAR`"]
268 #[inline(always)]
269 pub fn is_auto_clear(&self) -> bool {
270 *self == CLRCCONRX_A::AUTO_CLEAR
271 }
272}
273#[doc = "Field `CLRCCONRX` writer - Clear Continuous Clock."]
274pub type CLRCCONRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTL_SPEC, CLRCCONRX_A, O>;
275impl<'a, const O: u8> CLRCCONRX_W<'a, O> {
276 #[doc = "No effect. No effect on the CC bit."]
277 #[inline(always)]
278 pub fn no_effect(self) -> &'a mut W {
279 self.variant(CLRCCONRX_A::NO_EFFECT)
280 }
281 #[doc = "Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time."]
282 #[inline(always)]
283 pub fn auto_clear(self) -> &'a mut W {
284 self.variant(CLRCCONRX_A::AUTO_CLEAR)
285 }
286}
287impl R {
288 #[doc = "Bit 1 - Break Enable."]
289 #[inline(always)]
290 pub fn txbrken(&self) -> TXBRKEN_R {
291 TXBRKEN_R::new(((self.bits >> 1) & 1) != 0)
292 }
293 #[doc = "Bit 2 - Enable address detect mode."]
294 #[inline(always)]
295 pub fn addrdet(&self) -> ADDRDET_R {
296 ADDRDET_R::new(((self.bits >> 2) & 1) != 0)
297 }
298 #[doc = "Bit 6 - Transmit Disable."]
299 #[inline(always)]
300 pub fn txdis(&self) -> TXDIS_R {
301 TXDIS_R::new(((self.bits >> 6) & 1) != 0)
302 }
303 #[doc = "Bit 8 - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."]
304 #[inline(always)]
305 pub fn cc(&self) -> CC_R {
306 CC_R::new(((self.bits >> 8) & 1) != 0)
307 }
308 #[doc = "Bit 9 - Clear Continuous Clock."]
309 #[inline(always)]
310 pub fn clrcconrx(&self) -> CLRCCONRX_R {
311 CLRCCONRX_R::new(((self.bits >> 9) & 1) != 0)
312 }
313}
314impl W {
315 #[doc = "Bit 1 - Break Enable."]
316 #[inline(always)]
317 pub fn txbrken(&mut self) -> TXBRKEN_W<1> {
318 TXBRKEN_W::new(self)
319 }
320 #[doc = "Bit 2 - Enable address detect mode."]
321 #[inline(always)]
322 pub fn addrdet(&mut self) -> ADDRDET_W<2> {
323 ADDRDET_W::new(self)
324 }
325 #[doc = "Bit 6 - Transmit Disable."]
326 #[inline(always)]
327 pub fn txdis(&mut self) -> TXDIS_W<6> {
328 TXDIS_W::new(self)
329 }
330 #[doc = "Bit 8 - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode."]
331 #[inline(always)]
332 pub fn cc(&mut self) -> CC_W<8> {
333 CC_W::new(self)
334 }
335 #[doc = "Bit 9 - Clear Continuous Clock."]
336 #[inline(always)]
337 pub fn clrcconrx(&mut self) -> CLRCCONRX_W<9> {
338 CLRCCONRX_W::new(self)
339 }
340 #[doc = "Writes raw bits to the register."]
341 #[inline(always)]
342 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
343 self.0.bits(bits);
344 self
345 }
346}
347#[doc = "USART Control register. USART control settings that are more likely to change during operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl](index.html) module"]
348pub struct CTL_SPEC;
349impl crate::RegisterSpec for CTL_SPEC {
350 type Ux = u32;
351}
352#[doc = "`read()` method returns [ctl::R](R) reader structure"]
353impl crate::Readable for CTL_SPEC {
354 type Reader = R;
355}
356#[doc = "`write(|w| ..)` method takes [ctl::W](W) writer structure"]
357impl crate::Writable for CTL_SPEC {
358 type Writer = W;
359}
360#[doc = "`reset()` method sets CTL to value 0"]
361impl crate::Resettable for CTL_SPEC {
362 #[inline(always)]
363 fn reset_value() -> Self::Ux {
364 0
365 }
366}