Struct lpc81x_pac::lpc811::spi0::txdatctl::R

source ·
pub struct R(_);
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Register TXDATCTL reader

Implementations§

Bits 0:15 - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.

Bit 16 - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register.

Bit 20 - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.

Bit 21 - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.

Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA.

Bits 24:27 - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. … 0xF = Data transfer is 16 bits in length.

Methods from Deref<Target = R<TXDATCTL_SPEC>>§

Reads raw bits from register.

Trait Implementations§

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

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