Struct lpc81x_pac::lpc812::spi0::div::R

pub struct R(_);

Register DIV reader

Implementations

impl R

pub fn divval(&self) -> DIVVAL_R

Bits 0:15 - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

Methods from Deref<Target = R<DIV_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<DIV_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<DIV_SPEC>> for R

fn from(reader: R<DIV_SPEC>) -> Self

Converts to this type from the input type.