Struct lpc81x_pac::spi0::txdatctl::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn txdat(&mut self) -> _TXDATW

Bits 0:15 - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.

pub fn txsseln(&mut self) -> _TXSSELNW

Bit 16 - Transmit Slave Select . This field controls what is output for SSEL in master mode. The active state of the SSEL function is configured by bits in the CFG register.

pub fn eot(&mut self) -> _EOTW

Bit 20 - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register.

pub fn eof(&mut self) -> _EOFW

Bit 21 - End of Frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.

pub fn rxignore(&mut self) -> _RXIGNOREW

Bit 22 - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process.

pub fn flen(&mut self) -> _FLENW

Bits 24:27 - Frame Length. Specifies the frame length from 1 to 16 bits. Note that frame lengths greater than 16 bits are supported by multiple sequential frames Note that if a 1-bit frame is selected, the master function will always insert a delay with a length of one SCK time following the single clock seen on the SCK pin. 0x0 = Data frame is 1 bit in length. 0x1 = Data frame is 1 bit in length. 0x2 = Data frame is 3 bits in length. ... 0xF = Data frame is 16 bits in length.