1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Memory Remap control register"]
5 pub memoryremap: MEMORYREMAP,
6 _reserved1: [u8; 12usize],
7 #[doc = "0x10 - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest"]
8 pub ahbmatprio: AHBMATPRIO,
9 _reserved2: [u8; 36usize],
10 #[doc = "0x38 - System tick calibration for secure part of CPU0"]
11 pub cpu0stckcal: CPU0STCKCAL,
12 #[doc = "0x3c - System tick calibration for non-secure part of CPU0"]
13 pub cpu0nstckcal: CPU0NSTCKCAL,
14 #[doc = "0x40 - System tick calibration for CPU1"]
15 pub cpu1stckcal: CPU1STCKCAL,
16 _reserved5: [u8; 4usize],
17 #[doc = "0x48 - NMI Source Select"]
18 pub nmisrc: NMISRC,
19 _reserved6: [u8; 180usize],
20 #[doc = "0x100 - Peripheral reset control 0"]
21 pub presetctrl0: PRESETCTRL0,
22 #[doc = "0x104 - Peripheral reset control 1"]
23 pub presetctrl1: PRESETCTRL1,
24 #[doc = "0x108 - Peripheral reset control 2"]
25 pub presetctrl2: PRESETCTRL2,
26 _reserved9: [u8; 20usize],
27 #[doc = "0x120 - Peripheral reset control set register"]
28 pub presetctrlset: [PRESETCTRLSET; 3],
29 _reserved10: [u8; 20usize],
30 #[doc = "0x140 - Peripheral reset control clear register"]
31 pub presetctrlclr: [PRESETCTRLCLR; 3],
32 _reserved11: [u8; 20usize],
33 #[doc = "0x160 - generate a software_reset"]
34 pub swr_reset: SWR_RESET,
35 _reserved12: [u8; 156usize],
36 #[doc = "0x200 - AHB Clock control 0"]
37 pub ahbclkctrl0: AHBCLKCTRL0,
38 #[doc = "0x204 - AHB Clock control 1"]
39 pub ahbclkctrl1: AHBCLKCTRL1,
40 #[doc = "0x208 - AHB Clock control 2"]
41 pub ahbclkctrl2: AHBCLKCTRL2,
42 _reserved15: [u8; 20usize],
43 #[doc = "0x220 - Peripheral reset control register"]
44 pub ahbclkctrlset: [AHBCLKCTRLSET; 3],
45 _reserved16: [u8; 20usize],
46 #[doc = "0x240 - Peripheral reset control register"]
47 pub ahbclkctrlclr: [AHBCLKCTRLCLR; 3],
48 _reserved17: [u8; 20usize],
49 _reserved_17_systickclksel0: [u8; 4usize],
50 _reserved_18_systickclksel1: [u8; 4usize],
51 #[doc = "0x268 - Trace clock source select"]
52 pub traceclksel: TRACECLKSEL,
53 _reserved_20_ctimerclksel0: [u8; 4usize],
54 _reserved_21_ctimerclksel1: [u8; 4usize],
55 _reserved_22_ctimerclksel2: [u8; 4usize],
56 _reserved_23_ctimerclksel3: [u8; 4usize],
57 _reserved_24_ctimerclksel4: [u8; 4usize],
58 #[doc = "0x280 - Main clock A source select"]
59 pub mainclksela: MAINCLKSELA,
60 #[doc = "0x284 - Main clock source select"]
61 pub mainclkselb: MAINCLKSELB,
62 #[doc = "0x288 - CLKOUT clock source select"]
63 pub clkoutsel: CLKOUTSEL,
64 _reserved28: [u8; 4usize],
65 #[doc = "0x290 - PLL0 clock source select"]
66 pub pll0clksel: PLL0CLKSEL,
67 #[doc = "0x294 - PLL1 clock source select"]
68 pub pll1clksel: PLL1CLKSEL,
69 _reserved30: [u8; 12usize],
70 #[doc = "0x2a4 - ADC clock source select"]
71 pub adcclksel: ADCCLKSEL,
72 #[doc = "0x2a8 - FS USB clock source select"]
73 pub usb0clksel: USB0CLKSEL,
74 _reserved32: [u8; 4usize],
75 _reserved_32_fcclksel0: [u8; 4usize],
76 _reserved_33_fcclksel1: [u8; 4usize],
77 _reserved_34_fcclksel2: [u8; 4usize],
78 _reserved_35_fcclksel3: [u8; 4usize],
79 _reserved_36_fcclksel4: [u8; 4usize],
80 _reserved_37_fcclksel5: [u8; 4usize],
81 _reserved_38_fcclksel6: [u8; 4usize],
82 _reserved_39_fcclksel7: [u8; 4usize],
83 #[doc = "0x2d0 - HS LSPI clock source select"]
84 pub hslspiclksel: HSLSPICLKSEL,
85 _reserved41: [u8; 12usize],
86 #[doc = "0x2e0 - MCLK clock source select"]
87 pub mclkclksel: MCLKCLKSEL,
88 _reserved42: [u8; 12usize],
89 #[doc = "0x2f0 - SCTimer/PWM clock source select"]
90 pub sctclksel: SCTCLKSEL,
91 _reserved43: [u8; 4usize],
92 #[doc = "0x2f8 - SDIO clock source select"]
93 pub sdioclksel: SDIOCLKSEL,
94 _reserved44: [u8; 4usize],
95 #[doc = "0x300 - System Tick Timer divider for CPU0"]
96 pub systickclkdiv0: SYSTICKCLKDIV0,
97 #[doc = "0x304 - System Tick Timer divider for CPU1"]
98 pub systickclkdiv1: SYSTICKCLKDIV1,
99 #[doc = "0x308 - TRACE clock divider"]
100 pub traceclkdiv: TRACECLKDIV,
101 _reserved47: [u8; 20usize],
102 _reserved_47_flexfrg0ctrl: [u8; 4usize],
103 _reserved_48_flexfrg1ctrl: [u8; 4usize],
104 _reserved_49_flexfrg2ctrl: [u8; 4usize],
105 _reserved_50_flexfrg3ctrl: [u8; 4usize],
106 _reserved_51_flexfrg4ctrl: [u8; 4usize],
107 _reserved_52_flexfrg5ctrl: [u8; 4usize],
108 _reserved_53_flexfrg6ctrl: [u8; 4usize],
109 _reserved_54_flexfrg7ctrl: [u8; 4usize],
110 _reserved55: [u8; 64usize],
111 #[doc = "0x380 - System clock divider"]
112 pub ahbclkdiv: AHBCLKDIV,
113 #[doc = "0x384 - CLKOUT clock divider"]
114 pub clkoutdiv: CLKOUTDIV,
115 #[doc = "0x388 - FRO_HF (96MHz) clock divider"]
116 pub frohfdiv: FROHFDIV,
117 #[doc = "0x38c - WDT clock divider"]
118 pub wdtclkdiv: WDTCLKDIV,
119 _reserved59: [u8; 4usize],
120 #[doc = "0x394 - ADC clock divider"]
121 pub adcclkdiv: ADCCLKDIV,
122 #[doc = "0x398 - USB0 Clock divider"]
123 pub usb0clkdiv: USB0CLKDIV,
124 _reserved61: [u8; 16usize],
125 #[doc = "0x3ac - I2S MCLK clock divider"]
126 pub mclkdiv: MCLKDIV,
127 _reserved62: [u8; 4usize],
128 #[doc = "0x3b4 - SCT/PWM clock divider"]
129 pub sctclkdiv: SCTCLKDIV,
130 _reserved63: [u8; 4usize],
131 #[doc = "0x3bc - SDIO clock divider"]
132 pub sdioclkdiv: SDIOCLKDIV,
133 _reserved64: [u8; 4usize],
134 #[doc = "0x3c4 - PLL0 clock divider"]
135 pub pll0clkdiv: PLL0CLKDIV,
136 _reserved65: [u8; 52usize],
137 #[doc = "0x3fc - Control clock configuration registers access (like xxxDIV, xxxSEL)"]
138 pub clockgenupdatelockout: CLOCKGENUPDATELOCKOUT,
139 #[doc = "0x400 - FMC configuration register"]
140 pub fmccr: FMCCR,
141 _reserved67: [u8; 8usize],
142 #[doc = "0x40c - USB0 need clock control"]
143 pub usb0needclkctrl: USB0NEEDCLKCTRL,
144 #[doc = "0x410 - USB0 need clock status"]
145 pub usb0needclkstat: USB0NEEDCLKSTAT,
146 _reserved69: [u8; 8usize],
147 #[doc = "0x41c - FMCflush control"]
148 pub fmcflush: FMCFLUSH,
149 #[doc = "0x420 - MCLK control"]
150 pub mclkio: MCLKIO,
151 #[doc = "0x424 - USB1 need clock control"]
152 pub usb1needclkctrl: USB1NEEDCLKCTRL,
153 #[doc = "0x428 - USB1 need clock status"]
154 pub usb1needclkstat: USB1NEEDCLKSTAT,
155 _reserved73: [u8; 52usize],
156 #[doc = "0x460 - SDIO CCLKIN phase and delay control"]
157 pub sdioclkctrl: SDIOCLKCTRL,
158 _reserved74: [u8; 252usize],
159 #[doc = "0x560 - PLL1 550m control"]
160 pub pll1ctrl: PLL1CTRL,
161 #[doc = "0x564 - PLL1 550m status"]
162 pub pll1stat: PLL1STAT,
163 #[doc = "0x568 - PLL1 550m N divider"]
164 pub pll1ndec: PLL1NDEC,
165 #[doc = "0x56c - PLL1 550m M divider"]
166 pub pll1mdec: PLL1MDEC,
167 #[doc = "0x570 - PLL1 550m P divider"]
168 pub pll1pdec: PLL1PDEC,
169 _reserved79: [u8; 12usize],
170 #[doc = "0x580 - PLL0 550m control"]
171 pub pll0ctrl: PLL0CTRL,
172 #[doc = "0x584 - PLL0 550m status"]
173 pub pll0stat: PLL0STAT,
174 #[doc = "0x588 - PLL0 550m N divider"]
175 pub pll0ndec: PLL0NDEC,
176 #[doc = "0x58c - PLL0 550m P divider"]
177 pub pll0pdec: PLL0PDEC,
178 #[doc = "0x590 - PLL0 Spread Spectrum Wrapper control register 0"]
179 pub pll0sscg0: PLL0SSCG0,
180 #[doc = "0x594 - PLL0 Spread Spectrum Wrapper control register 1"]
181 pub pll0sscg1: PLL0SSCG1,
182 _reserved85: [u8; 616usize],
183 #[doc = "0x800 - CPU Control for multiple processors"]
184 pub cpuctrl: CPUCTRL,
185 #[doc = "0x804 - Coprocessor Boot Address"]
186 pub cpboot: CPBOOT,
187 _reserved87: [u8; 4usize],
188 #[doc = "0x80c - CPU Status"]
189 pub cpstat: CPSTAT,
190 _reserved88: [u8; 520usize],
191 #[doc = "0xa18 - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures"]
192 pub clock_ctrl: CLOCK_CTRL,
193 _reserved89: [u8; 244usize],
194 #[doc = "0xb10 - Comparator Interrupt control"]
195 pub comp_int_ctrl: COMP_INT_CTRL,
196 #[doc = "0xb14 - Comparator Interrupt status"]
197 pub comp_int_status: COMP_INT_STATUS,
198 _reserved91: [u8; 748usize],
199 #[doc = "0xe04 - Control automatic clock gating"]
200 pub autoclkgateoverride: AUTOCLKGATEOVERRIDE,
201 #[doc = "0xe08 - Enable bypass of the first stage of synchonization inside GPIO_INT module"]
202 pub gpiopsync: GPIOPSYNC,
203 _reserved93: [u8; 404usize],
204 #[doc = "0xfa0 - Control write access to security registers."]
205 pub debug_lock_en: DEBUG_LOCK_EN,
206 #[doc = "0xfa4 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control."]
207 pub debug_features: DEBUG_FEATURES,
208 #[doc = "0xfa8 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register."]
209 pub debug_features_dp: DEBUG_FEATURES_DP,
210 _reserved96: [u8; 16usize],
211 #[doc = "0xfbc - block quiddikey/PUF all index."]
212 pub key_block: KEY_BLOCK,
213 #[doc = "0xfc0 - Debug authentication BEACON register"]
214 pub debug_auth_beacon: DEBUG_AUTH_BEACON,
215 _reserved98: [u8; 16usize],
216 #[doc = "0xfd4 - CPUs configuration register"]
217 pub cpucfg: CPUCFG,
218 _reserved99: [u8; 32usize],
219 #[doc = "0xff8 - Device ID"]
220 pub device_id0: DEVICE_ID0,
221 #[doc = "0xffc - Chip revision ID and Number"]
222 pub dieid: DIEID,
223}
224impl RegisterBlock {
225 #[doc = "0x260 - Peripheral reset control register"]
226 #[inline(always)]
227 pub fn systickclkselx0(&self) -> &SYSTICKCLKSELX0 {
228 unsafe { &*(((self as *const Self) as *const u8).add(608usize) as *const SYSTICKCLKSELX0) }
229 }
230 #[doc = "0x260 - Peripheral reset control register"]
231 #[inline(always)]
232 pub fn systickclkselx0_mut(&self) -> &mut SYSTICKCLKSELX0 {
233 unsafe { &mut *(((self as *const Self) as *mut u8).add(608usize) as *mut SYSTICKCLKSELX0) }
234 }
235 #[doc = "0x260 - System Tick Timer for CPU0 source select"]
236 #[inline(always)]
237 pub fn systickclksel0(&self) -> &SYSTICKCLKSEL0 {
238 unsafe { &*(((self as *const Self) as *const u8).add(608usize) as *const SYSTICKCLKSEL0) }
239 }
240 #[doc = "0x260 - System Tick Timer for CPU0 source select"]
241 #[inline(always)]
242 pub fn systickclksel0_mut(&self) -> &mut SYSTICKCLKSEL0 {
243 unsafe { &mut *(((self as *const Self) as *mut u8).add(608usize) as *mut SYSTICKCLKSEL0) }
244 }
245 #[doc = "0x264 - Peripheral reset control register"]
246 #[inline(always)]
247 pub fn systickclkselx1(&self) -> &SYSTICKCLKSELX1 {
248 unsafe { &*(((self as *const Self) as *const u8).add(612usize) as *const SYSTICKCLKSELX1) }
249 }
250 #[doc = "0x264 - Peripheral reset control register"]
251 #[inline(always)]
252 pub fn systickclkselx1_mut(&self) -> &mut SYSTICKCLKSELX1 {
253 unsafe { &mut *(((self as *const Self) as *mut u8).add(612usize) as *mut SYSTICKCLKSELX1) }
254 }
255 #[doc = "0x264 - System Tick Timer for CPU1 source select"]
256 #[inline(always)]
257 pub fn systickclksel1(&self) -> &SYSTICKCLKSEL1 {
258 unsafe { &*(((self as *const Self) as *const u8).add(612usize) as *const SYSTICKCLKSEL1) }
259 }
260 #[doc = "0x264 - System Tick Timer for CPU1 source select"]
261 #[inline(always)]
262 pub fn systickclksel1_mut(&self) -> &mut SYSTICKCLKSEL1 {
263 unsafe { &mut *(((self as *const Self) as *mut u8).add(612usize) as *mut SYSTICKCLKSEL1) }
264 }
265 #[doc = "0x26c - Peripheral reset control register"]
266 #[inline(always)]
267 pub fn ctimerclkselx0(&self) -> &CTIMERCLKSELX0 {
268 unsafe { &*(((self as *const Self) as *const u8).add(620usize) as *const CTIMERCLKSELX0) }
269 }
270 #[doc = "0x26c - Peripheral reset control register"]
271 #[inline(always)]
272 pub fn ctimerclkselx0_mut(&self) -> &mut CTIMERCLKSELX0 {
273 unsafe { &mut *(((self as *const Self) as *mut u8).add(620usize) as *mut CTIMERCLKSELX0) }
274 }
275 #[doc = "0x26c - CTimer 0 clock source select"]
276 #[inline(always)]
277 pub fn ctimerclksel0(&self) -> &CTIMERCLKSEL0 {
278 unsafe { &*(((self as *const Self) as *const u8).add(620usize) as *const CTIMERCLKSEL0) }
279 }
280 #[doc = "0x26c - CTimer 0 clock source select"]
281 #[inline(always)]
282 pub fn ctimerclksel0_mut(&self) -> &mut CTIMERCLKSEL0 {
283 unsafe { &mut *(((self as *const Self) as *mut u8).add(620usize) as *mut CTIMERCLKSEL0) }
284 }
285 #[doc = "0x270 - Peripheral reset control register"]
286 #[inline(always)]
287 pub fn ctimerclkselx1(&self) -> &CTIMERCLKSELX1 {
288 unsafe { &*(((self as *const Self) as *const u8).add(624usize) as *const CTIMERCLKSELX1) }
289 }
290 #[doc = "0x270 - Peripheral reset control register"]
291 #[inline(always)]
292 pub fn ctimerclkselx1_mut(&self) -> &mut CTIMERCLKSELX1 {
293 unsafe { &mut *(((self as *const Self) as *mut u8).add(624usize) as *mut CTIMERCLKSELX1) }
294 }
295 #[doc = "0x270 - CTimer 1 clock source select"]
296 #[inline(always)]
297 pub fn ctimerclksel1(&self) -> &CTIMERCLKSEL1 {
298 unsafe { &*(((self as *const Self) as *const u8).add(624usize) as *const CTIMERCLKSEL1) }
299 }
300 #[doc = "0x270 - CTimer 1 clock source select"]
301 #[inline(always)]
302 pub fn ctimerclksel1_mut(&self) -> &mut CTIMERCLKSEL1 {
303 unsafe { &mut *(((self as *const Self) as *mut u8).add(624usize) as *mut CTIMERCLKSEL1) }
304 }
305 #[doc = "0x274 - Peripheral reset control register"]
306 #[inline(always)]
307 pub fn ctimerclkselx2(&self) -> &CTIMERCLKSELX2 {
308 unsafe { &*(((self as *const Self) as *const u8).add(628usize) as *const CTIMERCLKSELX2) }
309 }
310 #[doc = "0x274 - Peripheral reset control register"]
311 #[inline(always)]
312 pub fn ctimerclkselx2_mut(&self) -> &mut CTIMERCLKSELX2 {
313 unsafe { &mut *(((self as *const Self) as *mut u8).add(628usize) as *mut CTIMERCLKSELX2) }
314 }
315 #[doc = "0x274 - CTimer 2 clock source select"]
316 #[inline(always)]
317 pub fn ctimerclksel2(&self) -> &CTIMERCLKSEL2 {
318 unsafe { &*(((self as *const Self) as *const u8).add(628usize) as *const CTIMERCLKSEL2) }
319 }
320 #[doc = "0x274 - CTimer 2 clock source select"]
321 #[inline(always)]
322 pub fn ctimerclksel2_mut(&self) -> &mut CTIMERCLKSEL2 {
323 unsafe { &mut *(((self as *const Self) as *mut u8).add(628usize) as *mut CTIMERCLKSEL2) }
324 }
325 #[doc = "0x278 - Peripheral reset control register"]
326 #[inline(always)]
327 pub fn ctimerclkselx3(&self) -> &CTIMERCLKSELX3 {
328 unsafe { &*(((self as *const Self) as *const u8).add(632usize) as *const CTIMERCLKSELX3) }
329 }
330 #[doc = "0x278 - Peripheral reset control register"]
331 #[inline(always)]
332 pub fn ctimerclkselx3_mut(&self) -> &mut CTIMERCLKSELX3 {
333 unsafe { &mut *(((self as *const Self) as *mut u8).add(632usize) as *mut CTIMERCLKSELX3) }
334 }
335 #[doc = "0x278 - CTimer 3 clock source select"]
336 #[inline(always)]
337 pub fn ctimerclksel3(&self) -> &CTIMERCLKSEL3 {
338 unsafe { &*(((self as *const Self) as *const u8).add(632usize) as *const CTIMERCLKSEL3) }
339 }
340 #[doc = "0x278 - CTimer 3 clock source select"]
341 #[inline(always)]
342 pub fn ctimerclksel3_mut(&self) -> &mut CTIMERCLKSEL3 {
343 unsafe { &mut *(((self as *const Self) as *mut u8).add(632usize) as *mut CTIMERCLKSEL3) }
344 }
345 #[doc = "0x27c - Peripheral reset control register"]
346 #[inline(always)]
347 pub fn ctimerclkselx4(&self) -> &CTIMERCLKSELX4 {
348 unsafe { &*(((self as *const Self) as *const u8).add(636usize) as *const CTIMERCLKSELX4) }
349 }
350 #[doc = "0x27c - Peripheral reset control register"]
351 #[inline(always)]
352 pub fn ctimerclkselx4_mut(&self) -> &mut CTIMERCLKSELX4 {
353 unsafe { &mut *(((self as *const Self) as *mut u8).add(636usize) as *mut CTIMERCLKSELX4) }
354 }
355 #[doc = "0x27c - CTimer 4 clock source select"]
356 #[inline(always)]
357 pub fn ctimerclksel4(&self) -> &CTIMERCLKSEL4 {
358 unsafe { &*(((self as *const Self) as *const u8).add(636usize) as *const CTIMERCLKSEL4) }
359 }
360 #[doc = "0x27c - CTimer 4 clock source select"]
361 #[inline(always)]
362 pub fn ctimerclksel4_mut(&self) -> &mut CTIMERCLKSEL4 {
363 unsafe { &mut *(((self as *const Self) as *mut u8).add(636usize) as *mut CTIMERCLKSEL4) }
364 }
365 #[doc = "0x2b0 - Peripheral reset control register"]
366 #[inline(always)]
367 pub fn fcclkselx0(&self) -> &FCCLKSELX0 {
368 unsafe { &*(((self as *const Self) as *const u8).add(688usize) as *const FCCLKSELX0) }
369 }
370 #[doc = "0x2b0 - Peripheral reset control register"]
371 #[inline(always)]
372 pub fn fcclkselx0_mut(&self) -> &mut FCCLKSELX0 {
373 unsafe { &mut *(((self as *const Self) as *mut u8).add(688usize) as *mut FCCLKSELX0) }
374 }
375 #[doc = "0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider"]
376 #[inline(always)]
377 pub fn fcclksel0(&self) -> &FCCLKSEL0 {
378 unsafe { &*(((self as *const Self) as *const u8).add(688usize) as *const FCCLKSEL0) }
379 }
380 #[doc = "0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider"]
381 #[inline(always)]
382 pub fn fcclksel0_mut(&self) -> &mut FCCLKSEL0 {
383 unsafe { &mut *(((self as *const Self) as *mut u8).add(688usize) as *mut FCCLKSEL0) }
384 }
385 #[doc = "0x2b4 - Peripheral reset control register"]
386 #[inline(always)]
387 pub fn fcclkselx1(&self) -> &FCCLKSELX1 {
388 unsafe { &*(((self as *const Self) as *const u8).add(692usize) as *const FCCLKSELX1) }
389 }
390 #[doc = "0x2b4 - Peripheral reset control register"]
391 #[inline(always)]
392 pub fn fcclkselx1_mut(&self) -> &mut FCCLKSELX1 {
393 unsafe { &mut *(((self as *const Self) as *mut u8).add(692usize) as *mut FCCLKSELX1) }
394 }
395 #[doc = "0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider"]
396 #[inline(always)]
397 pub fn fcclksel1(&self) -> &FCCLKSEL1 {
398 unsafe { &*(((self as *const Self) as *const u8).add(692usize) as *const FCCLKSEL1) }
399 }
400 #[doc = "0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider"]
401 #[inline(always)]
402 pub fn fcclksel1_mut(&self) -> &mut FCCLKSEL1 {
403 unsafe { &mut *(((self as *const Self) as *mut u8).add(692usize) as *mut FCCLKSEL1) }
404 }
405 #[doc = "0x2b8 - Peripheral reset control register"]
406 #[inline(always)]
407 pub fn fcclkselx2(&self) -> &FCCLKSELX2 {
408 unsafe { &*(((self as *const Self) as *const u8).add(696usize) as *const FCCLKSELX2) }
409 }
410 #[doc = "0x2b8 - Peripheral reset control register"]
411 #[inline(always)]
412 pub fn fcclkselx2_mut(&self) -> &mut FCCLKSELX2 {
413 unsafe { &mut *(((self as *const Self) as *mut u8).add(696usize) as *mut FCCLKSELX2) }
414 }
415 #[doc = "0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider"]
416 #[inline(always)]
417 pub fn fcclksel2(&self) -> &FCCLKSEL2 {
418 unsafe { &*(((self as *const Self) as *const u8).add(696usize) as *const FCCLKSEL2) }
419 }
420 #[doc = "0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider"]
421 #[inline(always)]
422 pub fn fcclksel2_mut(&self) -> &mut FCCLKSEL2 {
423 unsafe { &mut *(((self as *const Self) as *mut u8).add(696usize) as *mut FCCLKSEL2) }
424 }
425 #[doc = "0x2bc - Peripheral reset control register"]
426 #[inline(always)]
427 pub fn fcclkselx3(&self) -> &FCCLKSELX3 {
428 unsafe { &*(((self as *const Self) as *const u8).add(700usize) as *const FCCLKSELX3) }
429 }
430 #[doc = "0x2bc - Peripheral reset control register"]
431 #[inline(always)]
432 pub fn fcclkselx3_mut(&self) -> &mut FCCLKSELX3 {
433 unsafe { &mut *(((self as *const Self) as *mut u8).add(700usize) as *mut FCCLKSELX3) }
434 }
435 #[doc = "0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider"]
436 #[inline(always)]
437 pub fn fcclksel3(&self) -> &FCCLKSEL3 {
438 unsafe { &*(((self as *const Self) as *const u8).add(700usize) as *const FCCLKSEL3) }
439 }
440 #[doc = "0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider"]
441 #[inline(always)]
442 pub fn fcclksel3_mut(&self) -> &mut FCCLKSEL3 {
443 unsafe { &mut *(((self as *const Self) as *mut u8).add(700usize) as *mut FCCLKSEL3) }
444 }
445 #[doc = "0x2c0 - Peripheral reset control register"]
446 #[inline(always)]
447 pub fn fcclkselx4(&self) -> &FCCLKSELX4 {
448 unsafe { &*(((self as *const Self) as *const u8).add(704usize) as *const FCCLKSELX4) }
449 }
450 #[doc = "0x2c0 - Peripheral reset control register"]
451 #[inline(always)]
452 pub fn fcclkselx4_mut(&self) -> &mut FCCLKSELX4 {
453 unsafe { &mut *(((self as *const Self) as *mut u8).add(704usize) as *mut FCCLKSELX4) }
454 }
455 #[doc = "0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider"]
456 #[inline(always)]
457 pub fn fcclksel4(&self) -> &FCCLKSEL4 {
458 unsafe { &*(((self as *const Self) as *const u8).add(704usize) as *const FCCLKSEL4) }
459 }
460 #[doc = "0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider"]
461 #[inline(always)]
462 pub fn fcclksel4_mut(&self) -> &mut FCCLKSEL4 {
463 unsafe { &mut *(((self as *const Self) as *mut u8).add(704usize) as *mut FCCLKSEL4) }
464 }
465 #[doc = "0x2c4 - Peripheral reset control register"]
466 #[inline(always)]
467 pub fn fcclkselx5(&self) -> &FCCLKSELX5 {
468 unsafe { &*(((self as *const Self) as *const u8).add(708usize) as *const FCCLKSELX5) }
469 }
470 #[doc = "0x2c4 - Peripheral reset control register"]
471 #[inline(always)]
472 pub fn fcclkselx5_mut(&self) -> &mut FCCLKSELX5 {
473 unsafe { &mut *(((self as *const Self) as *mut u8).add(708usize) as *mut FCCLKSELX5) }
474 }
475 #[doc = "0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider"]
476 #[inline(always)]
477 pub fn fcclksel5(&self) -> &FCCLKSEL5 {
478 unsafe { &*(((self as *const Self) as *const u8).add(708usize) as *const FCCLKSEL5) }
479 }
480 #[doc = "0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider"]
481 #[inline(always)]
482 pub fn fcclksel5_mut(&self) -> &mut FCCLKSEL5 {
483 unsafe { &mut *(((self as *const Self) as *mut u8).add(708usize) as *mut FCCLKSEL5) }
484 }
485 #[doc = "0x2c8 - Peripheral reset control register"]
486 #[inline(always)]
487 pub fn fcclkselx6(&self) -> &FCCLKSELX6 {
488 unsafe { &*(((self as *const Self) as *const u8).add(712usize) as *const FCCLKSELX6) }
489 }
490 #[doc = "0x2c8 - Peripheral reset control register"]
491 #[inline(always)]
492 pub fn fcclkselx6_mut(&self) -> &mut FCCLKSELX6 {
493 unsafe { &mut *(((self as *const Self) as *mut u8).add(712usize) as *mut FCCLKSELX6) }
494 }
495 #[doc = "0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider"]
496 #[inline(always)]
497 pub fn fcclksel6(&self) -> &FCCLKSEL6 {
498 unsafe { &*(((self as *const Self) as *const u8).add(712usize) as *const FCCLKSEL6) }
499 }
500 #[doc = "0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider"]
501 #[inline(always)]
502 pub fn fcclksel6_mut(&self) -> &mut FCCLKSEL6 {
503 unsafe { &mut *(((self as *const Self) as *mut u8).add(712usize) as *mut FCCLKSEL6) }
504 }
505 #[doc = "0x2cc - Peripheral reset control register"]
506 #[inline(always)]
507 pub fn fcclkselx7(&self) -> &FCCLKSELX7 {
508 unsafe { &*(((self as *const Self) as *const u8).add(716usize) as *const FCCLKSELX7) }
509 }
510 #[doc = "0x2cc - Peripheral reset control register"]
511 #[inline(always)]
512 pub fn fcclkselx7_mut(&self) -> &mut FCCLKSELX7 {
513 unsafe { &mut *(((self as *const Self) as *mut u8).add(716usize) as *mut FCCLKSELX7) }
514 }
515 #[doc = "0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider"]
516 #[inline(always)]
517 pub fn fcclksel7(&self) -> &FCCLKSEL7 {
518 unsafe { &*(((self as *const Self) as *const u8).add(716usize) as *const FCCLKSEL7) }
519 }
520 #[doc = "0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider"]
521 #[inline(always)]
522 pub fn fcclksel7_mut(&self) -> &mut FCCLKSEL7 {
523 unsafe { &mut *(((self as *const Self) as *mut u8).add(716usize) as *mut FCCLKSEL7) }
524 }
525 #[doc = "0x320 - Peripheral reset control register"]
526 #[inline(always)]
527 pub fn flexfrgxctrl0(&self) -> &FLEXFRGXCTRL0 {
528 unsafe { &*(((self as *const Self) as *const u8).add(800usize) as *const FLEXFRGXCTRL0) }
529 }
530 #[doc = "0x320 - Peripheral reset control register"]
531 #[inline(always)]
532 pub fn flexfrgxctrl0_mut(&self) -> &mut FLEXFRGXCTRL0 {
533 unsafe { &mut *(((self as *const Self) as *mut u8).add(800usize) as *mut FLEXFRGXCTRL0) }
534 }
535 #[doc = "0x320 - Fractional rate divider for flexcomm 0"]
536 #[inline(always)]
537 pub fn flexfrg0ctrl(&self) -> &FLEXFRG0CTRL {
538 unsafe { &*(((self as *const Self) as *const u8).add(800usize) as *const FLEXFRG0CTRL) }
539 }
540 #[doc = "0x320 - Fractional rate divider for flexcomm 0"]
541 #[inline(always)]
542 pub fn flexfrg0ctrl_mut(&self) -> &mut FLEXFRG0CTRL {
543 unsafe { &mut *(((self as *const Self) as *mut u8).add(800usize) as *mut FLEXFRG0CTRL) }
544 }
545 #[doc = "0x324 - Peripheral reset control register"]
546 #[inline(always)]
547 pub fn flexfrgxctrl1(&self) -> &FLEXFRGXCTRL1 {
548 unsafe { &*(((self as *const Self) as *const u8).add(804usize) as *const FLEXFRGXCTRL1) }
549 }
550 #[doc = "0x324 - Peripheral reset control register"]
551 #[inline(always)]
552 pub fn flexfrgxctrl1_mut(&self) -> &mut FLEXFRGXCTRL1 {
553 unsafe { &mut *(((self as *const Self) as *mut u8).add(804usize) as *mut FLEXFRGXCTRL1) }
554 }
555 #[doc = "0x324 - Fractional rate divider for flexcomm 1"]
556 #[inline(always)]
557 pub fn flexfrg1ctrl(&self) -> &FLEXFRG1CTRL {
558 unsafe { &*(((self as *const Self) as *const u8).add(804usize) as *const FLEXFRG1CTRL) }
559 }
560 #[doc = "0x324 - Fractional rate divider for flexcomm 1"]
561 #[inline(always)]
562 pub fn flexfrg1ctrl_mut(&self) -> &mut FLEXFRG1CTRL {
563 unsafe { &mut *(((self as *const Self) as *mut u8).add(804usize) as *mut FLEXFRG1CTRL) }
564 }
565 #[doc = "0x328 - Peripheral reset control register"]
566 #[inline(always)]
567 pub fn flexfrgxctrl2(&self) -> &FLEXFRGXCTRL2 {
568 unsafe { &*(((self as *const Self) as *const u8).add(808usize) as *const FLEXFRGXCTRL2) }
569 }
570 #[doc = "0x328 - Peripheral reset control register"]
571 #[inline(always)]
572 pub fn flexfrgxctrl2_mut(&self) -> &mut FLEXFRGXCTRL2 {
573 unsafe { &mut *(((self as *const Self) as *mut u8).add(808usize) as *mut FLEXFRGXCTRL2) }
574 }
575 #[doc = "0x328 - Fractional rate divider for flexcomm 2"]
576 #[inline(always)]
577 pub fn flexfrg2ctrl(&self) -> &FLEXFRG2CTRL {
578 unsafe { &*(((self as *const Self) as *const u8).add(808usize) as *const FLEXFRG2CTRL) }
579 }
580 #[doc = "0x328 - Fractional rate divider for flexcomm 2"]
581 #[inline(always)]
582 pub fn flexfrg2ctrl_mut(&self) -> &mut FLEXFRG2CTRL {
583 unsafe { &mut *(((self as *const Self) as *mut u8).add(808usize) as *mut FLEXFRG2CTRL) }
584 }
585 #[doc = "0x32c - Peripheral reset control register"]
586 #[inline(always)]
587 pub fn flexfrgxctrl3(&self) -> &FLEXFRGXCTRL3 {
588 unsafe { &*(((self as *const Self) as *const u8).add(812usize) as *const FLEXFRGXCTRL3) }
589 }
590 #[doc = "0x32c - Peripheral reset control register"]
591 #[inline(always)]
592 pub fn flexfrgxctrl3_mut(&self) -> &mut FLEXFRGXCTRL3 {
593 unsafe { &mut *(((self as *const Self) as *mut u8).add(812usize) as *mut FLEXFRGXCTRL3) }
594 }
595 #[doc = "0x32c - Fractional rate divider for flexcomm 3"]
596 #[inline(always)]
597 pub fn flexfrg3ctrl(&self) -> &FLEXFRG3CTRL {
598 unsafe { &*(((self as *const Self) as *const u8).add(812usize) as *const FLEXFRG3CTRL) }
599 }
600 #[doc = "0x32c - Fractional rate divider for flexcomm 3"]
601 #[inline(always)]
602 pub fn flexfrg3ctrl_mut(&self) -> &mut FLEXFRG3CTRL {
603 unsafe { &mut *(((self as *const Self) as *mut u8).add(812usize) as *mut FLEXFRG3CTRL) }
604 }
605 #[doc = "0x330 - Peripheral reset control register"]
606 #[inline(always)]
607 pub fn flexfrgxctrl4(&self) -> &FLEXFRGXCTRL4 {
608 unsafe { &*(((self as *const Self) as *const u8).add(816usize) as *const FLEXFRGXCTRL4) }
609 }
610 #[doc = "0x330 - Peripheral reset control register"]
611 #[inline(always)]
612 pub fn flexfrgxctrl4_mut(&self) -> &mut FLEXFRGXCTRL4 {
613 unsafe { &mut *(((self as *const Self) as *mut u8).add(816usize) as *mut FLEXFRGXCTRL4) }
614 }
615 #[doc = "0x330 - Fractional rate divider for flexcomm 4"]
616 #[inline(always)]
617 pub fn flexfrg4ctrl(&self) -> &FLEXFRG4CTRL {
618 unsafe { &*(((self as *const Self) as *const u8).add(816usize) as *const FLEXFRG4CTRL) }
619 }
620 #[doc = "0x330 - Fractional rate divider for flexcomm 4"]
621 #[inline(always)]
622 pub fn flexfrg4ctrl_mut(&self) -> &mut FLEXFRG4CTRL {
623 unsafe { &mut *(((self as *const Self) as *mut u8).add(816usize) as *mut FLEXFRG4CTRL) }
624 }
625 #[doc = "0x334 - Peripheral reset control register"]
626 #[inline(always)]
627 pub fn flexfrgxctrl5(&self) -> &FLEXFRGXCTRL5 {
628 unsafe { &*(((self as *const Self) as *const u8).add(820usize) as *const FLEXFRGXCTRL5) }
629 }
630 #[doc = "0x334 - Peripheral reset control register"]
631 #[inline(always)]
632 pub fn flexfrgxctrl5_mut(&self) -> &mut FLEXFRGXCTRL5 {
633 unsafe { &mut *(((self as *const Self) as *mut u8).add(820usize) as *mut FLEXFRGXCTRL5) }
634 }
635 #[doc = "0x334 - Fractional rate divider for flexcomm 5"]
636 #[inline(always)]
637 pub fn flexfrg5ctrl(&self) -> &FLEXFRG5CTRL {
638 unsafe { &*(((self as *const Self) as *const u8).add(820usize) as *const FLEXFRG5CTRL) }
639 }
640 #[doc = "0x334 - Fractional rate divider for flexcomm 5"]
641 #[inline(always)]
642 pub fn flexfrg5ctrl_mut(&self) -> &mut FLEXFRG5CTRL {
643 unsafe { &mut *(((self as *const Self) as *mut u8).add(820usize) as *mut FLEXFRG5CTRL) }
644 }
645 #[doc = "0x338 - Peripheral reset control register"]
646 #[inline(always)]
647 pub fn flexfrgxctrl6(&self) -> &FLEXFRGXCTRL6 {
648 unsafe { &*(((self as *const Self) as *const u8).add(824usize) as *const FLEXFRGXCTRL6) }
649 }
650 #[doc = "0x338 - Peripheral reset control register"]
651 #[inline(always)]
652 pub fn flexfrgxctrl6_mut(&self) -> &mut FLEXFRGXCTRL6 {
653 unsafe { &mut *(((self as *const Self) as *mut u8).add(824usize) as *mut FLEXFRGXCTRL6) }
654 }
655 #[doc = "0x338 - Fractional rate divider for flexcomm 6"]
656 #[inline(always)]
657 pub fn flexfrg6ctrl(&self) -> &FLEXFRG6CTRL {
658 unsafe { &*(((self as *const Self) as *const u8).add(824usize) as *const FLEXFRG6CTRL) }
659 }
660 #[doc = "0x338 - Fractional rate divider for flexcomm 6"]
661 #[inline(always)]
662 pub fn flexfrg6ctrl_mut(&self) -> &mut FLEXFRG6CTRL {
663 unsafe { &mut *(((self as *const Self) as *mut u8).add(824usize) as *mut FLEXFRG6CTRL) }
664 }
665 #[doc = "0x33c - Peripheral reset control register"]
666 #[inline(always)]
667 pub fn flexfrgxctrl7(&self) -> &FLEXFRGXCTRL7 {
668 unsafe { &*(((self as *const Self) as *const u8).add(828usize) as *const FLEXFRGXCTRL7) }
669 }
670 #[doc = "0x33c - Peripheral reset control register"]
671 #[inline(always)]
672 pub fn flexfrgxctrl7_mut(&self) -> &mut FLEXFRGXCTRL7 {
673 unsafe { &mut *(((self as *const Self) as *mut u8).add(828usize) as *mut FLEXFRGXCTRL7) }
674 }
675 #[doc = "0x33c - Fractional rate divider for flexcomm 7"]
676 #[inline(always)]
677 pub fn flexfrg7ctrl(&self) -> &FLEXFRG7CTRL {
678 unsafe { &*(((self as *const Self) as *const u8).add(828usize) as *const FLEXFRG7CTRL) }
679 }
680 #[doc = "0x33c - Fractional rate divider for flexcomm 7"]
681 #[inline(always)]
682 pub fn flexfrg7ctrl_mut(&self) -> &mut FLEXFRG7CTRL {
683 unsafe { &mut *(((self as *const Self) as *mut u8).add(828usize) as *mut FLEXFRG7CTRL) }
684 }
685}
686#[doc = "Memory Remap control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memoryremap](memoryremap) module"]
687pub type MEMORYREMAP = crate::Reg<u32, _MEMORYREMAP>;
688#[allow(missing_docs)]
689#[doc(hidden)]
690pub struct _MEMORYREMAP;
691#[doc = "`read()` method returns [memoryremap::R](memoryremap::R) reader structure"]
692impl crate::Readable for MEMORYREMAP {}
693#[doc = "`write(|w| ..)` method takes [memoryremap::W](memoryremap::W) writer structure"]
694impl crate::Writable for MEMORYREMAP {}
695#[doc = "Memory Remap control register"]
696pub mod memoryremap;
697#[doc = "AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmatprio](ahbmatprio) module"]
698pub type AHBMATPRIO = crate::Reg<u32, _AHBMATPRIO>;
699#[allow(missing_docs)]
700#[doc(hidden)]
701pub struct _AHBMATPRIO;
702#[doc = "`read()` method returns [ahbmatprio::R](ahbmatprio::R) reader structure"]
703impl crate::Readable for AHBMATPRIO {}
704#[doc = "`write(|w| ..)` method takes [ahbmatprio::W](ahbmatprio::W) writer structure"]
705impl crate::Writable for AHBMATPRIO {}
706#[doc = "AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest"]
707pub mod ahbmatprio;
708#[doc = "System tick calibration for secure part of CPU0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu0stckcal](cpu0stckcal) module"]
709pub type CPU0STCKCAL = crate::Reg<u32, _CPU0STCKCAL>;
710#[allow(missing_docs)]
711#[doc(hidden)]
712pub struct _CPU0STCKCAL;
713#[doc = "`read()` method returns [cpu0stckcal::R](cpu0stckcal::R) reader structure"]
714impl crate::Readable for CPU0STCKCAL {}
715#[doc = "`write(|w| ..)` method takes [cpu0stckcal::W](cpu0stckcal::W) writer structure"]
716impl crate::Writable for CPU0STCKCAL {}
717#[doc = "System tick calibration for secure part of CPU0"]
718pub mod cpu0stckcal;
719#[doc = "System tick calibration for non-secure part of CPU0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu0nstckcal](cpu0nstckcal) module"]
720pub type CPU0NSTCKCAL = crate::Reg<u32, _CPU0NSTCKCAL>;
721#[allow(missing_docs)]
722#[doc(hidden)]
723pub struct _CPU0NSTCKCAL;
724#[doc = "`read()` method returns [cpu0nstckcal::R](cpu0nstckcal::R) reader structure"]
725impl crate::Readable for CPU0NSTCKCAL {}
726#[doc = "`write(|w| ..)` method takes [cpu0nstckcal::W](cpu0nstckcal::W) writer structure"]
727impl crate::Writable for CPU0NSTCKCAL {}
728#[doc = "System tick calibration for non-secure part of CPU0"]
729pub mod cpu0nstckcal;
730#[doc = "System tick calibration for CPU1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu1stckcal](cpu1stckcal) module"]
731pub type CPU1STCKCAL = crate::Reg<u32, _CPU1STCKCAL>;
732#[allow(missing_docs)]
733#[doc(hidden)]
734pub struct _CPU1STCKCAL;
735#[doc = "`read()` method returns [cpu1stckcal::R](cpu1stckcal::R) reader structure"]
736impl crate::Readable for CPU1STCKCAL {}
737#[doc = "`write(|w| ..)` method takes [cpu1stckcal::W](cpu1stckcal::W) writer structure"]
738impl crate::Writable for CPU1STCKCAL {}
739#[doc = "System tick calibration for CPU1"]
740pub mod cpu1stckcal;
741#[doc = "NMI Source Select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmisrc](nmisrc) module"]
742pub type NMISRC = crate::Reg<u32, _NMISRC>;
743#[allow(missing_docs)]
744#[doc(hidden)]
745pub struct _NMISRC;
746#[doc = "`read()` method returns [nmisrc::R](nmisrc::R) reader structure"]
747impl crate::Readable for NMISRC {}
748#[doc = "`write(|w| ..)` method takes [nmisrc::W](nmisrc::W) writer structure"]
749impl crate::Writable for NMISRC {}
750#[doc = "NMI Source Select"]
751pub mod nmisrc;
752#[doc = "Peripheral reset control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl0](presetctrl0) module"]
753pub type PRESETCTRL0 = crate::Reg<u32, _PRESETCTRL0>;
754#[allow(missing_docs)]
755#[doc(hidden)]
756pub struct _PRESETCTRL0;
757#[doc = "`read()` method returns [presetctrl0::R](presetctrl0::R) reader structure"]
758impl crate::Readable for PRESETCTRL0 {}
759#[doc = "`write(|w| ..)` method takes [presetctrl0::W](presetctrl0::W) writer structure"]
760impl crate::Writable for PRESETCTRL0 {}
761#[doc = "Peripheral reset control 0"]
762pub mod presetctrl0;
763#[doc = "Peripheral reset control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl1](presetctrl1) module"]
764pub type PRESETCTRL1 = crate::Reg<u32, _PRESETCTRL1>;
765#[allow(missing_docs)]
766#[doc(hidden)]
767pub struct _PRESETCTRL1;
768#[doc = "`read()` method returns [presetctrl1::R](presetctrl1::R) reader structure"]
769impl crate::Readable for PRESETCTRL1 {}
770#[doc = "`write(|w| ..)` method takes [presetctrl1::W](presetctrl1::W) writer structure"]
771impl crate::Writable for PRESETCTRL1 {}
772#[doc = "Peripheral reset control 1"]
773pub mod presetctrl1;
774#[doc = "Peripheral reset control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrl2](presetctrl2) module"]
775pub type PRESETCTRL2 = crate::Reg<u32, _PRESETCTRL2>;
776#[allow(missing_docs)]
777#[doc(hidden)]
778pub struct _PRESETCTRL2;
779#[doc = "`read()` method returns [presetctrl2::R](presetctrl2::R) reader structure"]
780impl crate::Readable for PRESETCTRL2 {}
781#[doc = "`write(|w| ..)` method takes [presetctrl2::W](presetctrl2::W) writer structure"]
782impl crate::Writable for PRESETCTRL2 {}
783#[doc = "Peripheral reset control 2"]
784pub mod presetctrl2;
785#[doc = "Peripheral reset control set register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrlset](presetctrlset) module"]
786pub type PRESETCTRLSET = crate::Reg<u32, _PRESETCTRLSET>;
787#[allow(missing_docs)]
788#[doc(hidden)]
789pub struct _PRESETCTRLSET;
790#[doc = "`read()` method returns [presetctrlset::R](presetctrlset::R) reader structure"]
791impl crate::Readable for PRESETCTRLSET {}
792#[doc = "`write(|w| ..)` method takes [presetctrlset::W](presetctrlset::W) writer structure"]
793impl crate::Writable for PRESETCTRLSET {}
794#[doc = "Peripheral reset control set register"]
795pub mod presetctrlset;
796#[doc = "Peripheral reset control clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [presetctrlclr](presetctrlclr) module"]
797pub type PRESETCTRLCLR = crate::Reg<u32, _PRESETCTRLCLR>;
798#[allow(missing_docs)]
799#[doc(hidden)]
800pub struct _PRESETCTRLCLR;
801#[doc = "`read()` method returns [presetctrlclr::R](presetctrlclr::R) reader structure"]
802impl crate::Readable for PRESETCTRLCLR {}
803#[doc = "`write(|w| ..)` method takes [presetctrlclr::W](presetctrlclr::W) writer structure"]
804impl crate::Writable for PRESETCTRLCLR {}
805#[doc = "Peripheral reset control clear register"]
806pub mod presetctrlclr;
807#[doc = "generate a software_reset\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swr_reset](swr_reset) module"]
808pub type SWR_RESET = crate::Reg<u32, _SWR_RESET>;
809#[allow(missing_docs)]
810#[doc(hidden)]
811pub struct _SWR_RESET;
812#[doc = "`write(|w| ..)` method takes [swr_reset::W](swr_reset::W) writer structure"]
813impl crate::Writable for SWR_RESET {}
814#[doc = "generate a software_reset"]
815pub mod swr_reset;
816#[doc = "AHB Clock control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl0](ahbclkctrl0) module"]
817pub type AHBCLKCTRL0 = crate::Reg<u32, _AHBCLKCTRL0>;
818#[allow(missing_docs)]
819#[doc(hidden)]
820pub struct _AHBCLKCTRL0;
821#[doc = "`read()` method returns [ahbclkctrl0::R](ahbclkctrl0::R) reader structure"]
822impl crate::Readable for AHBCLKCTRL0 {}
823#[doc = "`write(|w| ..)` method takes [ahbclkctrl0::W](ahbclkctrl0::W) writer structure"]
824impl crate::Writable for AHBCLKCTRL0 {}
825#[doc = "AHB Clock control 0"]
826pub mod ahbclkctrl0;
827#[doc = "AHB Clock control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl1](ahbclkctrl1) module"]
828pub type AHBCLKCTRL1 = crate::Reg<u32, _AHBCLKCTRL1>;
829#[allow(missing_docs)]
830#[doc(hidden)]
831pub struct _AHBCLKCTRL1;
832#[doc = "`read()` method returns [ahbclkctrl1::R](ahbclkctrl1::R) reader structure"]
833impl crate::Readable for AHBCLKCTRL1 {}
834#[doc = "`write(|w| ..)` method takes [ahbclkctrl1::W](ahbclkctrl1::W) writer structure"]
835impl crate::Writable for AHBCLKCTRL1 {}
836#[doc = "AHB Clock control 1"]
837pub mod ahbclkctrl1;
838#[doc = "AHB Clock control 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrl2](ahbclkctrl2) module"]
839pub type AHBCLKCTRL2 = crate::Reg<u32, _AHBCLKCTRL2>;
840#[allow(missing_docs)]
841#[doc(hidden)]
842pub struct _AHBCLKCTRL2;
843#[doc = "`read()` method returns [ahbclkctrl2::R](ahbclkctrl2::R) reader structure"]
844impl crate::Readable for AHBCLKCTRL2 {}
845#[doc = "`write(|w| ..)` method takes [ahbclkctrl2::W](ahbclkctrl2::W) writer structure"]
846impl crate::Writable for AHBCLKCTRL2 {}
847#[doc = "AHB Clock control 2"]
848pub mod ahbclkctrl2;
849#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrlset](ahbclkctrlset) module"]
850pub type AHBCLKCTRLSET = crate::Reg<u32, _AHBCLKCTRLSET>;
851#[allow(missing_docs)]
852#[doc(hidden)]
853pub struct _AHBCLKCTRLSET;
854#[doc = "`read()` method returns [ahbclkctrlset::R](ahbclkctrlset::R) reader structure"]
855impl crate::Readable for AHBCLKCTRLSET {}
856#[doc = "`write(|w| ..)` method takes [ahbclkctrlset::W](ahbclkctrlset::W) writer structure"]
857impl crate::Writable for AHBCLKCTRLSET {}
858#[doc = "Peripheral reset control register"]
859pub mod ahbclkctrlset;
860#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkctrlclr](ahbclkctrlclr) module"]
861pub type AHBCLKCTRLCLR = crate::Reg<u32, _AHBCLKCTRLCLR>;
862#[allow(missing_docs)]
863#[doc(hidden)]
864pub struct _AHBCLKCTRLCLR;
865#[doc = "`read()` method returns [ahbclkctrlclr::R](ahbclkctrlclr::R) reader structure"]
866impl crate::Readable for AHBCLKCTRLCLR {}
867#[doc = "`write(|w| ..)` method takes [ahbclkctrlclr::W](ahbclkctrlclr::W) writer structure"]
868impl crate::Writable for AHBCLKCTRLCLR {}
869#[doc = "Peripheral reset control register"]
870pub mod ahbclkctrlclr;
871#[doc = "System Tick Timer for CPU0 source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclksel0](systickclksel0) module"]
872pub type SYSTICKCLKSEL0 = crate::Reg<u32, _SYSTICKCLKSEL0>;
873#[allow(missing_docs)]
874#[doc(hidden)]
875pub struct _SYSTICKCLKSEL0;
876#[doc = "`read()` method returns [systickclksel0::R](systickclksel0::R) reader structure"]
877impl crate::Readable for SYSTICKCLKSEL0 {}
878#[doc = "`write(|w| ..)` method takes [systickclksel0::W](systickclksel0::W) writer structure"]
879impl crate::Writable for SYSTICKCLKSEL0 {}
880#[doc = "System Tick Timer for CPU0 source select"]
881pub mod systickclksel0;
882#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclkselx0](systickclkselx0) module"]
883pub type SYSTICKCLKSELX0 = crate::Reg<u32, _SYSTICKCLKSELX0>;
884#[allow(missing_docs)]
885#[doc(hidden)]
886pub struct _SYSTICKCLKSELX0;
887#[doc = "`read()` method returns [systickclkselx0::R](systickclkselx0::R) reader structure"]
888impl crate::Readable for SYSTICKCLKSELX0 {}
889#[doc = "`write(|w| ..)` method takes [systickclkselx0::W](systickclkselx0::W) writer structure"]
890impl crate::Writable for SYSTICKCLKSELX0 {}
891#[doc = "Peripheral reset control register"]
892pub mod systickclkselx0;
893#[doc = "System Tick Timer for CPU1 source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclksel1](systickclksel1) module"]
894pub type SYSTICKCLKSEL1 = crate::Reg<u32, _SYSTICKCLKSEL1>;
895#[allow(missing_docs)]
896#[doc(hidden)]
897pub struct _SYSTICKCLKSEL1;
898#[doc = "`read()` method returns [systickclksel1::R](systickclksel1::R) reader structure"]
899impl crate::Readable for SYSTICKCLKSEL1 {}
900#[doc = "`write(|w| ..)` method takes [systickclksel1::W](systickclksel1::W) writer structure"]
901impl crate::Writable for SYSTICKCLKSEL1 {}
902#[doc = "System Tick Timer for CPU1 source select"]
903pub mod systickclksel1;
904#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclkselx1](systickclkselx1) module"]
905pub type SYSTICKCLKSELX1 = crate::Reg<u32, _SYSTICKCLKSELX1>;
906#[allow(missing_docs)]
907#[doc(hidden)]
908pub struct _SYSTICKCLKSELX1;
909#[doc = "`read()` method returns [systickclkselx1::R](systickclkselx1::R) reader structure"]
910impl crate::Readable for SYSTICKCLKSELX1 {}
911#[doc = "`write(|w| ..)` method takes [systickclkselx1::W](systickclkselx1::W) writer structure"]
912impl crate::Writable for SYSTICKCLKSELX1 {}
913#[doc = "Peripheral reset control register"]
914pub mod systickclkselx1;
915#[doc = "Trace clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceclksel](traceclksel) module"]
916pub type TRACECLKSEL = crate::Reg<u32, _TRACECLKSEL>;
917#[allow(missing_docs)]
918#[doc(hidden)]
919pub struct _TRACECLKSEL;
920#[doc = "`read()` method returns [traceclksel::R](traceclksel::R) reader structure"]
921impl crate::Readable for TRACECLKSEL {}
922#[doc = "`write(|w| ..)` method takes [traceclksel::W](traceclksel::W) writer structure"]
923impl crate::Writable for TRACECLKSEL {}
924#[doc = "Trace clock source select"]
925pub mod traceclksel;
926#[doc = "CTimer 0 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel0](ctimerclksel0) module"]
927pub type CTIMERCLKSEL0 = crate::Reg<u32, _CTIMERCLKSEL0>;
928#[allow(missing_docs)]
929#[doc(hidden)]
930pub struct _CTIMERCLKSEL0;
931#[doc = "`read()` method returns [ctimerclksel0::R](ctimerclksel0::R) reader structure"]
932impl crate::Readable for CTIMERCLKSEL0 {}
933#[doc = "`write(|w| ..)` method takes [ctimerclksel0::W](ctimerclksel0::W) writer structure"]
934impl crate::Writable for CTIMERCLKSEL0 {}
935#[doc = "CTimer 0 clock source select"]
936pub mod ctimerclksel0;
937#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclkselx0](ctimerclkselx0) module"]
938pub type CTIMERCLKSELX0 = crate::Reg<u32, _CTIMERCLKSELX0>;
939#[allow(missing_docs)]
940#[doc(hidden)]
941pub struct _CTIMERCLKSELX0;
942#[doc = "`read()` method returns [ctimerclkselx0::R](ctimerclkselx0::R) reader structure"]
943impl crate::Readable for CTIMERCLKSELX0 {}
944#[doc = "`write(|w| ..)` method takes [ctimerclkselx0::W](ctimerclkselx0::W) writer structure"]
945impl crate::Writable for CTIMERCLKSELX0 {}
946#[doc = "Peripheral reset control register"]
947pub mod ctimerclkselx0;
948#[doc = "CTimer 1 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel1](ctimerclksel1) module"]
949pub type CTIMERCLKSEL1 = crate::Reg<u32, _CTIMERCLKSEL1>;
950#[allow(missing_docs)]
951#[doc(hidden)]
952pub struct _CTIMERCLKSEL1;
953#[doc = "`read()` method returns [ctimerclksel1::R](ctimerclksel1::R) reader structure"]
954impl crate::Readable for CTIMERCLKSEL1 {}
955#[doc = "`write(|w| ..)` method takes [ctimerclksel1::W](ctimerclksel1::W) writer structure"]
956impl crate::Writable for CTIMERCLKSEL1 {}
957#[doc = "CTimer 1 clock source select"]
958pub mod ctimerclksel1;
959#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclkselx1](ctimerclkselx1) module"]
960pub type CTIMERCLKSELX1 = crate::Reg<u32, _CTIMERCLKSELX1>;
961#[allow(missing_docs)]
962#[doc(hidden)]
963pub struct _CTIMERCLKSELX1;
964#[doc = "`read()` method returns [ctimerclkselx1::R](ctimerclkselx1::R) reader structure"]
965impl crate::Readable for CTIMERCLKSELX1 {}
966#[doc = "`write(|w| ..)` method takes [ctimerclkselx1::W](ctimerclkselx1::W) writer structure"]
967impl crate::Writable for CTIMERCLKSELX1 {}
968#[doc = "Peripheral reset control register"]
969pub mod ctimerclkselx1;
970#[doc = "CTimer 2 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel2](ctimerclksel2) module"]
971pub type CTIMERCLKSEL2 = crate::Reg<u32, _CTIMERCLKSEL2>;
972#[allow(missing_docs)]
973#[doc(hidden)]
974pub struct _CTIMERCLKSEL2;
975#[doc = "`read()` method returns [ctimerclksel2::R](ctimerclksel2::R) reader structure"]
976impl crate::Readable for CTIMERCLKSEL2 {}
977#[doc = "`write(|w| ..)` method takes [ctimerclksel2::W](ctimerclksel2::W) writer structure"]
978impl crate::Writable for CTIMERCLKSEL2 {}
979#[doc = "CTimer 2 clock source select"]
980pub mod ctimerclksel2;
981#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclkselx2](ctimerclkselx2) module"]
982pub type CTIMERCLKSELX2 = crate::Reg<u32, _CTIMERCLKSELX2>;
983#[allow(missing_docs)]
984#[doc(hidden)]
985pub struct _CTIMERCLKSELX2;
986#[doc = "`read()` method returns [ctimerclkselx2::R](ctimerclkselx2::R) reader structure"]
987impl crate::Readable for CTIMERCLKSELX2 {}
988#[doc = "`write(|w| ..)` method takes [ctimerclkselx2::W](ctimerclkselx2::W) writer structure"]
989impl crate::Writable for CTIMERCLKSELX2 {}
990#[doc = "Peripheral reset control register"]
991pub mod ctimerclkselx2;
992#[doc = "CTimer 3 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel3](ctimerclksel3) module"]
993pub type CTIMERCLKSEL3 = crate::Reg<u32, _CTIMERCLKSEL3>;
994#[allow(missing_docs)]
995#[doc(hidden)]
996pub struct _CTIMERCLKSEL3;
997#[doc = "`read()` method returns [ctimerclksel3::R](ctimerclksel3::R) reader structure"]
998impl crate::Readable for CTIMERCLKSEL3 {}
999#[doc = "`write(|w| ..)` method takes [ctimerclksel3::W](ctimerclksel3::W) writer structure"]
1000impl crate::Writable for CTIMERCLKSEL3 {}
1001#[doc = "CTimer 3 clock source select"]
1002pub mod ctimerclksel3;
1003#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclkselx3](ctimerclkselx3) module"]
1004pub type CTIMERCLKSELX3 = crate::Reg<u32, _CTIMERCLKSELX3>;
1005#[allow(missing_docs)]
1006#[doc(hidden)]
1007pub struct _CTIMERCLKSELX3;
1008#[doc = "`read()` method returns [ctimerclkselx3::R](ctimerclkselx3::R) reader structure"]
1009impl crate::Readable for CTIMERCLKSELX3 {}
1010#[doc = "`write(|w| ..)` method takes [ctimerclkselx3::W](ctimerclkselx3::W) writer structure"]
1011impl crate::Writable for CTIMERCLKSELX3 {}
1012#[doc = "Peripheral reset control register"]
1013pub mod ctimerclkselx3;
1014#[doc = "CTimer 4 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclksel4](ctimerclksel4) module"]
1015pub type CTIMERCLKSEL4 = crate::Reg<u32, _CTIMERCLKSEL4>;
1016#[allow(missing_docs)]
1017#[doc(hidden)]
1018pub struct _CTIMERCLKSEL4;
1019#[doc = "`read()` method returns [ctimerclksel4::R](ctimerclksel4::R) reader structure"]
1020impl crate::Readable for CTIMERCLKSEL4 {}
1021#[doc = "`write(|w| ..)` method takes [ctimerclksel4::W](ctimerclksel4::W) writer structure"]
1022impl crate::Writable for CTIMERCLKSEL4 {}
1023#[doc = "CTimer 4 clock source select"]
1024pub mod ctimerclksel4;
1025#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctimerclkselx4](ctimerclkselx4) module"]
1026pub type CTIMERCLKSELX4 = crate::Reg<u32, _CTIMERCLKSELX4>;
1027#[allow(missing_docs)]
1028#[doc(hidden)]
1029pub struct _CTIMERCLKSELX4;
1030#[doc = "`read()` method returns [ctimerclkselx4::R](ctimerclkselx4::R) reader structure"]
1031impl crate::Readable for CTIMERCLKSELX4 {}
1032#[doc = "`write(|w| ..)` method takes [ctimerclkselx4::W](ctimerclkselx4::W) writer structure"]
1033impl crate::Writable for CTIMERCLKSELX4 {}
1034#[doc = "Peripheral reset control register"]
1035pub mod ctimerclkselx4;
1036#[doc = "Main clock A source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclksela](mainclksela) module"]
1037pub type MAINCLKSELA = crate::Reg<u32, _MAINCLKSELA>;
1038#[allow(missing_docs)]
1039#[doc(hidden)]
1040pub struct _MAINCLKSELA;
1041#[doc = "`read()` method returns [mainclksela::R](mainclksela::R) reader structure"]
1042impl crate::Readable for MAINCLKSELA {}
1043#[doc = "`write(|w| ..)` method takes [mainclksela::W](mainclksela::W) writer structure"]
1044impl crate::Writable for MAINCLKSELA {}
1045#[doc = "Main clock A source select"]
1046pub mod mainclksela;
1047#[doc = "Main clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclkselb](mainclkselb) module"]
1048pub type MAINCLKSELB = crate::Reg<u32, _MAINCLKSELB>;
1049#[allow(missing_docs)]
1050#[doc(hidden)]
1051pub struct _MAINCLKSELB;
1052#[doc = "`read()` method returns [mainclkselb::R](mainclkselb::R) reader structure"]
1053impl crate::Readable for MAINCLKSELB {}
1054#[doc = "`write(|w| ..)` method takes [mainclkselb::W](mainclkselb::W) writer structure"]
1055impl crate::Writable for MAINCLKSELB {}
1056#[doc = "Main clock source select"]
1057pub mod mainclkselb;
1058#[doc = "CLKOUT clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkoutsel](clkoutsel) module"]
1059pub type CLKOUTSEL = crate::Reg<u32, _CLKOUTSEL>;
1060#[allow(missing_docs)]
1061#[doc(hidden)]
1062pub struct _CLKOUTSEL;
1063#[doc = "`read()` method returns [clkoutsel::R](clkoutsel::R) reader structure"]
1064impl crate::Readable for CLKOUTSEL {}
1065#[doc = "`write(|w| ..)` method takes [clkoutsel::W](clkoutsel::W) writer structure"]
1066impl crate::Writable for CLKOUTSEL {}
1067#[doc = "CLKOUT clock source select"]
1068pub mod clkoutsel;
1069#[doc = "PLL0 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0clksel](pll0clksel) module"]
1070pub type PLL0CLKSEL = crate::Reg<u32, _PLL0CLKSEL>;
1071#[allow(missing_docs)]
1072#[doc(hidden)]
1073pub struct _PLL0CLKSEL;
1074#[doc = "`read()` method returns [pll0clksel::R](pll0clksel::R) reader structure"]
1075impl crate::Readable for PLL0CLKSEL {}
1076#[doc = "`write(|w| ..)` method takes [pll0clksel::W](pll0clksel::W) writer structure"]
1077impl crate::Writable for PLL0CLKSEL {}
1078#[doc = "PLL0 clock source select"]
1079pub mod pll0clksel;
1080#[doc = "PLL1 clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1clksel](pll1clksel) module"]
1081pub type PLL1CLKSEL = crate::Reg<u32, _PLL1CLKSEL>;
1082#[allow(missing_docs)]
1083#[doc(hidden)]
1084pub struct _PLL1CLKSEL;
1085#[doc = "`read()` method returns [pll1clksel::R](pll1clksel::R) reader structure"]
1086impl crate::Readable for PLL1CLKSEL {}
1087#[doc = "`write(|w| ..)` method takes [pll1clksel::W](pll1clksel::W) writer structure"]
1088impl crate::Writable for PLL1CLKSEL {}
1089#[doc = "PLL1 clock source select"]
1090pub mod pll1clksel;
1091#[doc = "ADC clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcclksel](adcclksel) module"]
1092pub type ADCCLKSEL = crate::Reg<u32, _ADCCLKSEL>;
1093#[allow(missing_docs)]
1094#[doc(hidden)]
1095pub struct _ADCCLKSEL;
1096#[doc = "`read()` method returns [adcclksel::R](adcclksel::R) reader structure"]
1097impl crate::Readable for ADCCLKSEL {}
1098#[doc = "`write(|w| ..)` method takes [adcclksel::W](adcclksel::W) writer structure"]
1099impl crate::Writable for ADCCLKSEL {}
1100#[doc = "ADC clock source select"]
1101pub mod adcclksel;
1102#[doc = "FS USB clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clksel](usb0clksel) module"]
1103pub type USB0CLKSEL = crate::Reg<u32, _USB0CLKSEL>;
1104#[allow(missing_docs)]
1105#[doc(hidden)]
1106pub struct _USB0CLKSEL;
1107#[doc = "`read()` method returns [usb0clksel::R](usb0clksel::R) reader structure"]
1108impl crate::Readable for USB0CLKSEL {}
1109#[doc = "`write(|w| ..)` method takes [usb0clksel::W](usb0clksel::W) writer structure"]
1110impl crate::Writable for USB0CLKSEL {}
1111#[doc = "FS USB clock source select"]
1112pub mod usb0clksel;
1113#[doc = "Flexcomm Interface 0 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel0](fcclksel0) module"]
1114pub type FCCLKSEL0 = crate::Reg<u32, _FCCLKSEL0>;
1115#[allow(missing_docs)]
1116#[doc(hidden)]
1117pub struct _FCCLKSEL0;
1118#[doc = "`read()` method returns [fcclksel0::R](fcclksel0::R) reader structure"]
1119impl crate::Readable for FCCLKSEL0 {}
1120#[doc = "`write(|w| ..)` method takes [fcclksel0::W](fcclksel0::W) writer structure"]
1121impl crate::Writable for FCCLKSEL0 {}
1122#[doc = "Flexcomm Interface 0 clock source select for Fractional Rate Divider"]
1123pub mod fcclksel0;
1124#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx0](fcclkselx0) module"]
1125pub type FCCLKSELX0 = crate::Reg<u32, _FCCLKSELX0>;
1126#[allow(missing_docs)]
1127#[doc(hidden)]
1128pub struct _FCCLKSELX0;
1129#[doc = "`read()` method returns [fcclkselx0::R](fcclkselx0::R) reader structure"]
1130impl crate::Readable for FCCLKSELX0 {}
1131#[doc = "`write(|w| ..)` method takes [fcclkselx0::W](fcclkselx0::W) writer structure"]
1132impl crate::Writable for FCCLKSELX0 {}
1133#[doc = "Peripheral reset control register"]
1134pub mod fcclkselx0;
1135#[doc = "Flexcomm Interface 1 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel1](fcclksel1) module"]
1136pub type FCCLKSEL1 = crate::Reg<u32, _FCCLKSEL1>;
1137#[allow(missing_docs)]
1138#[doc(hidden)]
1139pub struct _FCCLKSEL1;
1140#[doc = "`read()` method returns [fcclksel1::R](fcclksel1::R) reader structure"]
1141impl crate::Readable for FCCLKSEL1 {}
1142#[doc = "`write(|w| ..)` method takes [fcclksel1::W](fcclksel1::W) writer structure"]
1143impl crate::Writable for FCCLKSEL1 {}
1144#[doc = "Flexcomm Interface 1 clock source select for Fractional Rate Divider"]
1145pub mod fcclksel1;
1146#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx1](fcclkselx1) module"]
1147pub type FCCLKSELX1 = crate::Reg<u32, _FCCLKSELX1>;
1148#[allow(missing_docs)]
1149#[doc(hidden)]
1150pub struct _FCCLKSELX1;
1151#[doc = "`read()` method returns [fcclkselx1::R](fcclkselx1::R) reader structure"]
1152impl crate::Readable for FCCLKSELX1 {}
1153#[doc = "`write(|w| ..)` method takes [fcclkselx1::W](fcclkselx1::W) writer structure"]
1154impl crate::Writable for FCCLKSELX1 {}
1155#[doc = "Peripheral reset control register"]
1156pub mod fcclkselx1;
1157#[doc = "Flexcomm Interface 2 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel2](fcclksel2) module"]
1158pub type FCCLKSEL2 = crate::Reg<u32, _FCCLKSEL2>;
1159#[allow(missing_docs)]
1160#[doc(hidden)]
1161pub struct _FCCLKSEL2;
1162#[doc = "`read()` method returns [fcclksel2::R](fcclksel2::R) reader structure"]
1163impl crate::Readable for FCCLKSEL2 {}
1164#[doc = "`write(|w| ..)` method takes [fcclksel2::W](fcclksel2::W) writer structure"]
1165impl crate::Writable for FCCLKSEL2 {}
1166#[doc = "Flexcomm Interface 2 clock source select for Fractional Rate Divider"]
1167pub mod fcclksel2;
1168#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx2](fcclkselx2) module"]
1169pub type FCCLKSELX2 = crate::Reg<u32, _FCCLKSELX2>;
1170#[allow(missing_docs)]
1171#[doc(hidden)]
1172pub struct _FCCLKSELX2;
1173#[doc = "`read()` method returns [fcclkselx2::R](fcclkselx2::R) reader structure"]
1174impl crate::Readable for FCCLKSELX2 {}
1175#[doc = "`write(|w| ..)` method takes [fcclkselx2::W](fcclkselx2::W) writer structure"]
1176impl crate::Writable for FCCLKSELX2 {}
1177#[doc = "Peripheral reset control register"]
1178pub mod fcclkselx2;
1179#[doc = "Flexcomm Interface 3 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel3](fcclksel3) module"]
1180pub type FCCLKSEL3 = crate::Reg<u32, _FCCLKSEL3>;
1181#[allow(missing_docs)]
1182#[doc(hidden)]
1183pub struct _FCCLKSEL3;
1184#[doc = "`read()` method returns [fcclksel3::R](fcclksel3::R) reader structure"]
1185impl crate::Readable for FCCLKSEL3 {}
1186#[doc = "`write(|w| ..)` method takes [fcclksel3::W](fcclksel3::W) writer structure"]
1187impl crate::Writable for FCCLKSEL3 {}
1188#[doc = "Flexcomm Interface 3 clock source select for Fractional Rate Divider"]
1189pub mod fcclksel3;
1190#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx3](fcclkselx3) module"]
1191pub type FCCLKSELX3 = crate::Reg<u32, _FCCLKSELX3>;
1192#[allow(missing_docs)]
1193#[doc(hidden)]
1194pub struct _FCCLKSELX3;
1195#[doc = "`read()` method returns [fcclkselx3::R](fcclkselx3::R) reader structure"]
1196impl crate::Readable for FCCLKSELX3 {}
1197#[doc = "`write(|w| ..)` method takes [fcclkselx3::W](fcclkselx3::W) writer structure"]
1198impl crate::Writable for FCCLKSELX3 {}
1199#[doc = "Peripheral reset control register"]
1200pub mod fcclkselx3;
1201#[doc = "Flexcomm Interface 4 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel4](fcclksel4) module"]
1202pub type FCCLKSEL4 = crate::Reg<u32, _FCCLKSEL4>;
1203#[allow(missing_docs)]
1204#[doc(hidden)]
1205pub struct _FCCLKSEL4;
1206#[doc = "`read()` method returns [fcclksel4::R](fcclksel4::R) reader structure"]
1207impl crate::Readable for FCCLKSEL4 {}
1208#[doc = "`write(|w| ..)` method takes [fcclksel4::W](fcclksel4::W) writer structure"]
1209impl crate::Writable for FCCLKSEL4 {}
1210#[doc = "Flexcomm Interface 4 clock source select for Fractional Rate Divider"]
1211pub mod fcclksel4;
1212#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx4](fcclkselx4) module"]
1213pub type FCCLKSELX4 = crate::Reg<u32, _FCCLKSELX4>;
1214#[allow(missing_docs)]
1215#[doc(hidden)]
1216pub struct _FCCLKSELX4;
1217#[doc = "`read()` method returns [fcclkselx4::R](fcclkselx4::R) reader structure"]
1218impl crate::Readable for FCCLKSELX4 {}
1219#[doc = "`write(|w| ..)` method takes [fcclkselx4::W](fcclkselx4::W) writer structure"]
1220impl crate::Writable for FCCLKSELX4 {}
1221#[doc = "Peripheral reset control register"]
1222pub mod fcclkselx4;
1223#[doc = "Flexcomm Interface 5 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel5](fcclksel5) module"]
1224pub type FCCLKSEL5 = crate::Reg<u32, _FCCLKSEL5>;
1225#[allow(missing_docs)]
1226#[doc(hidden)]
1227pub struct _FCCLKSEL5;
1228#[doc = "`read()` method returns [fcclksel5::R](fcclksel5::R) reader structure"]
1229impl crate::Readable for FCCLKSEL5 {}
1230#[doc = "`write(|w| ..)` method takes [fcclksel5::W](fcclksel5::W) writer structure"]
1231impl crate::Writable for FCCLKSEL5 {}
1232#[doc = "Flexcomm Interface 5 clock source select for Fractional Rate Divider"]
1233pub mod fcclksel5;
1234#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx5](fcclkselx5) module"]
1235pub type FCCLKSELX5 = crate::Reg<u32, _FCCLKSELX5>;
1236#[allow(missing_docs)]
1237#[doc(hidden)]
1238pub struct _FCCLKSELX5;
1239#[doc = "`read()` method returns [fcclkselx5::R](fcclkselx5::R) reader structure"]
1240impl crate::Readable for FCCLKSELX5 {}
1241#[doc = "`write(|w| ..)` method takes [fcclkselx5::W](fcclkselx5::W) writer structure"]
1242impl crate::Writable for FCCLKSELX5 {}
1243#[doc = "Peripheral reset control register"]
1244pub mod fcclkselx5;
1245#[doc = "Flexcomm Interface 6 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel6](fcclksel6) module"]
1246pub type FCCLKSEL6 = crate::Reg<u32, _FCCLKSEL6>;
1247#[allow(missing_docs)]
1248#[doc(hidden)]
1249pub struct _FCCLKSEL6;
1250#[doc = "`read()` method returns [fcclksel6::R](fcclksel6::R) reader structure"]
1251impl crate::Readable for FCCLKSEL6 {}
1252#[doc = "`write(|w| ..)` method takes [fcclksel6::W](fcclksel6::W) writer structure"]
1253impl crate::Writable for FCCLKSEL6 {}
1254#[doc = "Flexcomm Interface 6 clock source select for Fractional Rate Divider"]
1255pub mod fcclksel6;
1256#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx6](fcclkselx6) module"]
1257pub type FCCLKSELX6 = crate::Reg<u32, _FCCLKSELX6>;
1258#[allow(missing_docs)]
1259#[doc(hidden)]
1260pub struct _FCCLKSELX6;
1261#[doc = "`read()` method returns [fcclkselx6::R](fcclkselx6::R) reader structure"]
1262impl crate::Readable for FCCLKSELX6 {}
1263#[doc = "`write(|w| ..)` method takes [fcclkselx6::W](fcclkselx6::W) writer structure"]
1264impl crate::Writable for FCCLKSELX6 {}
1265#[doc = "Peripheral reset control register"]
1266pub mod fcclkselx6;
1267#[doc = "Flexcomm Interface 7 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel7](fcclksel7) module"]
1268pub type FCCLKSEL7 = crate::Reg<u32, _FCCLKSEL7>;
1269#[allow(missing_docs)]
1270#[doc(hidden)]
1271pub struct _FCCLKSEL7;
1272#[doc = "`read()` method returns [fcclksel7::R](fcclksel7::R) reader structure"]
1273impl crate::Readable for FCCLKSEL7 {}
1274#[doc = "`write(|w| ..)` method takes [fcclksel7::W](fcclksel7::W) writer structure"]
1275impl crate::Writable for FCCLKSEL7 {}
1276#[doc = "Flexcomm Interface 7 clock source select for Fractional Rate Divider"]
1277pub mod fcclksel7;
1278#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclkselx7](fcclkselx7) module"]
1279pub type FCCLKSELX7 = crate::Reg<u32, _FCCLKSELX7>;
1280#[allow(missing_docs)]
1281#[doc(hidden)]
1282pub struct _FCCLKSELX7;
1283#[doc = "`read()` method returns [fcclkselx7::R](fcclkselx7::R) reader structure"]
1284impl crate::Readable for FCCLKSELX7 {}
1285#[doc = "`write(|w| ..)` method takes [fcclkselx7::W](fcclkselx7::W) writer structure"]
1286impl crate::Writable for FCCLKSELX7 {}
1287#[doc = "Peripheral reset control register"]
1288pub mod fcclkselx7;
1289#[doc = "HS LSPI clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hslspiclksel](hslspiclksel) module"]
1290pub type HSLSPICLKSEL = crate::Reg<u32, _HSLSPICLKSEL>;
1291#[allow(missing_docs)]
1292#[doc(hidden)]
1293pub struct _HSLSPICLKSEL;
1294#[doc = "`read()` method returns [hslspiclksel::R](hslspiclksel::R) reader structure"]
1295impl crate::Readable for HSLSPICLKSEL {}
1296#[doc = "`write(|w| ..)` method takes [hslspiclksel::W](hslspiclksel::W) writer structure"]
1297impl crate::Writable for HSLSPICLKSEL {}
1298#[doc = "HS LSPI clock source select"]
1299pub mod hslspiclksel;
1300#[doc = "MCLK clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkclksel](mclkclksel) module"]
1301pub type MCLKCLKSEL = crate::Reg<u32, _MCLKCLKSEL>;
1302#[allow(missing_docs)]
1303#[doc(hidden)]
1304pub struct _MCLKCLKSEL;
1305#[doc = "`read()` method returns [mclkclksel::R](mclkclksel::R) reader structure"]
1306impl crate::Readable for MCLKCLKSEL {}
1307#[doc = "`write(|w| ..)` method takes [mclkclksel::W](mclkclksel::W) writer structure"]
1308impl crate::Writable for MCLKCLKSEL {}
1309#[doc = "MCLK clock source select"]
1310pub mod mclkclksel;
1311#[doc = "SCTimer/PWM clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sctclksel](sctclksel) module"]
1312pub type SCTCLKSEL = crate::Reg<u32, _SCTCLKSEL>;
1313#[allow(missing_docs)]
1314#[doc(hidden)]
1315pub struct _SCTCLKSEL;
1316#[doc = "`read()` method returns [sctclksel::R](sctclksel::R) reader structure"]
1317impl crate::Readable for SCTCLKSEL {}
1318#[doc = "`write(|w| ..)` method takes [sctclksel::W](sctclksel::W) writer structure"]
1319impl crate::Writable for SCTCLKSEL {}
1320#[doc = "SCTimer/PWM clock source select"]
1321pub mod sctclksel;
1322#[doc = "SDIO clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclksel](sdioclksel) module"]
1323pub type SDIOCLKSEL = crate::Reg<u32, _SDIOCLKSEL>;
1324#[allow(missing_docs)]
1325#[doc(hidden)]
1326pub struct _SDIOCLKSEL;
1327#[doc = "`read()` method returns [sdioclksel::R](sdioclksel::R) reader structure"]
1328impl crate::Readable for SDIOCLKSEL {}
1329#[doc = "`write(|w| ..)` method takes [sdioclksel::W](sdioclksel::W) writer structure"]
1330impl crate::Writable for SDIOCLKSEL {}
1331#[doc = "SDIO clock source select"]
1332pub mod sdioclksel;
1333#[doc = "System Tick Timer divider for CPU0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclkdiv0](systickclkdiv0) module"]
1334pub type SYSTICKCLKDIV0 = crate::Reg<u32, _SYSTICKCLKDIV0>;
1335#[allow(missing_docs)]
1336#[doc(hidden)]
1337pub struct _SYSTICKCLKDIV0;
1338#[doc = "`read()` method returns [systickclkdiv0::R](systickclkdiv0::R) reader structure"]
1339impl crate::Readable for SYSTICKCLKDIV0 {}
1340#[doc = "`write(|w| ..)` method takes [systickclkdiv0::W](systickclkdiv0::W) writer structure"]
1341impl crate::Writable for SYSTICKCLKDIV0 {}
1342#[doc = "System Tick Timer divider for CPU0"]
1343pub mod systickclkdiv0;
1344#[doc = "System Tick Timer divider for CPU1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systickclkdiv1](systickclkdiv1) module"]
1345pub type SYSTICKCLKDIV1 = crate::Reg<u32, _SYSTICKCLKDIV1>;
1346#[allow(missing_docs)]
1347#[doc(hidden)]
1348pub struct _SYSTICKCLKDIV1;
1349#[doc = "`read()` method returns [systickclkdiv1::R](systickclkdiv1::R) reader structure"]
1350impl crate::Readable for SYSTICKCLKDIV1 {}
1351#[doc = "`write(|w| ..)` method takes [systickclkdiv1::W](systickclkdiv1::W) writer structure"]
1352impl crate::Writable for SYSTICKCLKDIV1 {}
1353#[doc = "System Tick Timer divider for CPU1"]
1354pub mod systickclkdiv1;
1355#[doc = "TRACE clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceclkdiv](traceclkdiv) module"]
1356pub type TRACECLKDIV = crate::Reg<u32, _TRACECLKDIV>;
1357#[allow(missing_docs)]
1358#[doc(hidden)]
1359pub struct _TRACECLKDIV;
1360#[doc = "`read()` method returns [traceclkdiv::R](traceclkdiv::R) reader structure"]
1361impl crate::Readable for TRACECLKDIV {}
1362#[doc = "`write(|w| ..)` method takes [traceclkdiv::W](traceclkdiv::W) writer structure"]
1363impl crate::Writable for TRACECLKDIV {}
1364#[doc = "TRACE clock divider"]
1365pub mod traceclkdiv;
1366#[doc = "Fractional rate divider for flexcomm 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg0ctrl](flexfrg0ctrl) module"]
1367pub type FLEXFRG0CTRL = crate::Reg<u32, _FLEXFRG0CTRL>;
1368#[allow(missing_docs)]
1369#[doc(hidden)]
1370pub struct _FLEXFRG0CTRL;
1371#[doc = "`read()` method returns [flexfrg0ctrl::R](flexfrg0ctrl::R) reader structure"]
1372impl crate::Readable for FLEXFRG0CTRL {}
1373#[doc = "`write(|w| ..)` method takes [flexfrg0ctrl::W](flexfrg0ctrl::W) writer structure"]
1374impl crate::Writable for FLEXFRG0CTRL {}
1375#[doc = "Fractional rate divider for flexcomm 0"]
1376pub mod flexfrg0ctrl;
1377#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl0](flexfrgxctrl0) module"]
1378pub type FLEXFRGXCTRL0 = crate::Reg<u32, _FLEXFRGXCTRL0>;
1379#[allow(missing_docs)]
1380#[doc(hidden)]
1381pub struct _FLEXFRGXCTRL0;
1382#[doc = "`read()` method returns [flexfrgxctrl0::R](flexfrgxctrl0::R) reader structure"]
1383impl crate::Readable for FLEXFRGXCTRL0 {}
1384#[doc = "`write(|w| ..)` method takes [flexfrgxctrl0::W](flexfrgxctrl0::W) writer structure"]
1385impl crate::Writable for FLEXFRGXCTRL0 {}
1386#[doc = "Peripheral reset control register"]
1387pub mod flexfrgxctrl0;
1388#[doc = "Fractional rate divider for flexcomm 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg1ctrl](flexfrg1ctrl) module"]
1389pub type FLEXFRG1CTRL = crate::Reg<u32, _FLEXFRG1CTRL>;
1390#[allow(missing_docs)]
1391#[doc(hidden)]
1392pub struct _FLEXFRG1CTRL;
1393#[doc = "`read()` method returns [flexfrg1ctrl::R](flexfrg1ctrl::R) reader structure"]
1394impl crate::Readable for FLEXFRG1CTRL {}
1395#[doc = "`write(|w| ..)` method takes [flexfrg1ctrl::W](flexfrg1ctrl::W) writer structure"]
1396impl crate::Writable for FLEXFRG1CTRL {}
1397#[doc = "Fractional rate divider for flexcomm 1"]
1398pub mod flexfrg1ctrl;
1399#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl1](flexfrgxctrl1) module"]
1400pub type FLEXFRGXCTRL1 = crate::Reg<u32, _FLEXFRGXCTRL1>;
1401#[allow(missing_docs)]
1402#[doc(hidden)]
1403pub struct _FLEXFRGXCTRL1;
1404#[doc = "`read()` method returns [flexfrgxctrl1::R](flexfrgxctrl1::R) reader structure"]
1405impl crate::Readable for FLEXFRGXCTRL1 {}
1406#[doc = "`write(|w| ..)` method takes [flexfrgxctrl1::W](flexfrgxctrl1::W) writer structure"]
1407impl crate::Writable for FLEXFRGXCTRL1 {}
1408#[doc = "Peripheral reset control register"]
1409pub mod flexfrgxctrl1;
1410#[doc = "Fractional rate divider for flexcomm 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg2ctrl](flexfrg2ctrl) module"]
1411pub type FLEXFRG2CTRL = crate::Reg<u32, _FLEXFRG2CTRL>;
1412#[allow(missing_docs)]
1413#[doc(hidden)]
1414pub struct _FLEXFRG2CTRL;
1415#[doc = "`read()` method returns [flexfrg2ctrl::R](flexfrg2ctrl::R) reader structure"]
1416impl crate::Readable for FLEXFRG2CTRL {}
1417#[doc = "`write(|w| ..)` method takes [flexfrg2ctrl::W](flexfrg2ctrl::W) writer structure"]
1418impl crate::Writable for FLEXFRG2CTRL {}
1419#[doc = "Fractional rate divider for flexcomm 2"]
1420pub mod flexfrg2ctrl;
1421#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl2](flexfrgxctrl2) module"]
1422pub type FLEXFRGXCTRL2 = crate::Reg<u32, _FLEXFRGXCTRL2>;
1423#[allow(missing_docs)]
1424#[doc(hidden)]
1425pub struct _FLEXFRGXCTRL2;
1426#[doc = "`read()` method returns [flexfrgxctrl2::R](flexfrgxctrl2::R) reader structure"]
1427impl crate::Readable for FLEXFRGXCTRL2 {}
1428#[doc = "`write(|w| ..)` method takes [flexfrgxctrl2::W](flexfrgxctrl2::W) writer structure"]
1429impl crate::Writable for FLEXFRGXCTRL2 {}
1430#[doc = "Peripheral reset control register"]
1431pub mod flexfrgxctrl2;
1432#[doc = "Fractional rate divider for flexcomm 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg3ctrl](flexfrg3ctrl) module"]
1433pub type FLEXFRG3CTRL = crate::Reg<u32, _FLEXFRG3CTRL>;
1434#[allow(missing_docs)]
1435#[doc(hidden)]
1436pub struct _FLEXFRG3CTRL;
1437#[doc = "`read()` method returns [flexfrg3ctrl::R](flexfrg3ctrl::R) reader structure"]
1438impl crate::Readable for FLEXFRG3CTRL {}
1439#[doc = "`write(|w| ..)` method takes [flexfrg3ctrl::W](flexfrg3ctrl::W) writer structure"]
1440impl crate::Writable for FLEXFRG3CTRL {}
1441#[doc = "Fractional rate divider for flexcomm 3"]
1442pub mod flexfrg3ctrl;
1443#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl3](flexfrgxctrl3) module"]
1444pub type FLEXFRGXCTRL3 = crate::Reg<u32, _FLEXFRGXCTRL3>;
1445#[allow(missing_docs)]
1446#[doc(hidden)]
1447pub struct _FLEXFRGXCTRL3;
1448#[doc = "`read()` method returns [flexfrgxctrl3::R](flexfrgxctrl3::R) reader structure"]
1449impl crate::Readable for FLEXFRGXCTRL3 {}
1450#[doc = "`write(|w| ..)` method takes [flexfrgxctrl3::W](flexfrgxctrl3::W) writer structure"]
1451impl crate::Writable for FLEXFRGXCTRL3 {}
1452#[doc = "Peripheral reset control register"]
1453pub mod flexfrgxctrl3;
1454#[doc = "Fractional rate divider for flexcomm 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg4ctrl](flexfrg4ctrl) module"]
1455pub type FLEXFRG4CTRL = crate::Reg<u32, _FLEXFRG4CTRL>;
1456#[allow(missing_docs)]
1457#[doc(hidden)]
1458pub struct _FLEXFRG4CTRL;
1459#[doc = "`read()` method returns [flexfrg4ctrl::R](flexfrg4ctrl::R) reader structure"]
1460impl crate::Readable for FLEXFRG4CTRL {}
1461#[doc = "`write(|w| ..)` method takes [flexfrg4ctrl::W](flexfrg4ctrl::W) writer structure"]
1462impl crate::Writable for FLEXFRG4CTRL {}
1463#[doc = "Fractional rate divider for flexcomm 4"]
1464pub mod flexfrg4ctrl;
1465#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl4](flexfrgxctrl4) module"]
1466pub type FLEXFRGXCTRL4 = crate::Reg<u32, _FLEXFRGXCTRL4>;
1467#[allow(missing_docs)]
1468#[doc(hidden)]
1469pub struct _FLEXFRGXCTRL4;
1470#[doc = "`read()` method returns [flexfrgxctrl4::R](flexfrgxctrl4::R) reader structure"]
1471impl crate::Readable for FLEXFRGXCTRL4 {}
1472#[doc = "`write(|w| ..)` method takes [flexfrgxctrl4::W](flexfrgxctrl4::W) writer structure"]
1473impl crate::Writable for FLEXFRGXCTRL4 {}
1474#[doc = "Peripheral reset control register"]
1475pub mod flexfrgxctrl4;
1476#[doc = "Fractional rate divider for flexcomm 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg5ctrl](flexfrg5ctrl) module"]
1477pub type FLEXFRG5CTRL = crate::Reg<u32, _FLEXFRG5CTRL>;
1478#[allow(missing_docs)]
1479#[doc(hidden)]
1480pub struct _FLEXFRG5CTRL;
1481#[doc = "`read()` method returns [flexfrg5ctrl::R](flexfrg5ctrl::R) reader structure"]
1482impl crate::Readable for FLEXFRG5CTRL {}
1483#[doc = "`write(|w| ..)` method takes [flexfrg5ctrl::W](flexfrg5ctrl::W) writer structure"]
1484impl crate::Writable for FLEXFRG5CTRL {}
1485#[doc = "Fractional rate divider for flexcomm 5"]
1486pub mod flexfrg5ctrl;
1487#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl5](flexfrgxctrl5) module"]
1488pub type FLEXFRGXCTRL5 = crate::Reg<u32, _FLEXFRGXCTRL5>;
1489#[allow(missing_docs)]
1490#[doc(hidden)]
1491pub struct _FLEXFRGXCTRL5;
1492#[doc = "`read()` method returns [flexfrgxctrl5::R](flexfrgxctrl5::R) reader structure"]
1493impl crate::Readable for FLEXFRGXCTRL5 {}
1494#[doc = "`write(|w| ..)` method takes [flexfrgxctrl5::W](flexfrgxctrl5::W) writer structure"]
1495impl crate::Writable for FLEXFRGXCTRL5 {}
1496#[doc = "Peripheral reset control register"]
1497pub mod flexfrgxctrl5;
1498#[doc = "Fractional rate divider for flexcomm 6\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg6ctrl](flexfrg6ctrl) module"]
1499pub type FLEXFRG6CTRL = crate::Reg<u32, _FLEXFRG6CTRL>;
1500#[allow(missing_docs)]
1501#[doc(hidden)]
1502pub struct _FLEXFRG6CTRL;
1503#[doc = "`read()` method returns [flexfrg6ctrl::R](flexfrg6ctrl::R) reader structure"]
1504impl crate::Readable for FLEXFRG6CTRL {}
1505#[doc = "`write(|w| ..)` method takes [flexfrg6ctrl::W](flexfrg6ctrl::W) writer structure"]
1506impl crate::Writable for FLEXFRG6CTRL {}
1507#[doc = "Fractional rate divider for flexcomm 6"]
1508pub mod flexfrg6ctrl;
1509#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl6](flexfrgxctrl6) module"]
1510pub type FLEXFRGXCTRL6 = crate::Reg<u32, _FLEXFRGXCTRL6>;
1511#[allow(missing_docs)]
1512#[doc(hidden)]
1513pub struct _FLEXFRGXCTRL6;
1514#[doc = "`read()` method returns [flexfrgxctrl6::R](flexfrgxctrl6::R) reader structure"]
1515impl crate::Readable for FLEXFRGXCTRL6 {}
1516#[doc = "`write(|w| ..)` method takes [flexfrgxctrl6::W](flexfrgxctrl6::W) writer structure"]
1517impl crate::Writable for FLEXFRGXCTRL6 {}
1518#[doc = "Peripheral reset control register"]
1519pub mod flexfrgxctrl6;
1520#[doc = "Fractional rate divider for flexcomm 7\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrg7ctrl](flexfrg7ctrl) module"]
1521pub type FLEXFRG7CTRL = crate::Reg<u32, _FLEXFRG7CTRL>;
1522#[allow(missing_docs)]
1523#[doc(hidden)]
1524pub struct _FLEXFRG7CTRL;
1525#[doc = "`read()` method returns [flexfrg7ctrl::R](flexfrg7ctrl::R) reader structure"]
1526impl crate::Readable for FLEXFRG7CTRL {}
1527#[doc = "`write(|w| ..)` method takes [flexfrg7ctrl::W](flexfrg7ctrl::W) writer structure"]
1528impl crate::Writable for FLEXFRG7CTRL {}
1529#[doc = "Fractional rate divider for flexcomm 7"]
1530pub mod flexfrg7ctrl;
1531#[doc = "Peripheral reset control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flexfrgxctrl7](flexfrgxctrl7) module"]
1532pub type FLEXFRGXCTRL7 = crate::Reg<u32, _FLEXFRGXCTRL7>;
1533#[allow(missing_docs)]
1534#[doc(hidden)]
1535pub struct _FLEXFRGXCTRL7;
1536#[doc = "`read()` method returns [flexfrgxctrl7::R](flexfrgxctrl7::R) reader structure"]
1537impl crate::Readable for FLEXFRGXCTRL7 {}
1538#[doc = "`write(|w| ..)` method takes [flexfrgxctrl7::W](flexfrgxctrl7::W) writer structure"]
1539impl crate::Writable for FLEXFRGXCTRL7 {}
1540#[doc = "Peripheral reset control register"]
1541pub mod flexfrgxctrl7;
1542#[doc = "System clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbclkdiv](ahbclkdiv) module"]
1543pub type AHBCLKDIV = crate::Reg<u32, _AHBCLKDIV>;
1544#[allow(missing_docs)]
1545#[doc(hidden)]
1546pub struct _AHBCLKDIV;
1547#[doc = "`read()` method returns [ahbclkdiv::R](ahbclkdiv::R) reader structure"]
1548impl crate::Readable for AHBCLKDIV {}
1549#[doc = "`write(|w| ..)` method takes [ahbclkdiv::W](ahbclkdiv::W) writer structure"]
1550impl crate::Writable for AHBCLKDIV {}
1551#[doc = "System clock divider"]
1552pub mod ahbclkdiv;
1553#[doc = "CLKOUT clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkoutdiv](clkoutdiv) module"]
1554pub type CLKOUTDIV = crate::Reg<u32, _CLKOUTDIV>;
1555#[allow(missing_docs)]
1556#[doc(hidden)]
1557pub struct _CLKOUTDIV;
1558#[doc = "`read()` method returns [clkoutdiv::R](clkoutdiv::R) reader structure"]
1559impl crate::Readable for CLKOUTDIV {}
1560#[doc = "`write(|w| ..)` method takes [clkoutdiv::W](clkoutdiv::W) writer structure"]
1561impl crate::Writable for CLKOUTDIV {}
1562#[doc = "CLKOUT clock divider"]
1563pub mod clkoutdiv;
1564#[doc = "FRO_HF (96MHz) clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frohfdiv](frohfdiv) module"]
1565pub type FROHFDIV = crate::Reg<u32, _FROHFDIV>;
1566#[allow(missing_docs)]
1567#[doc(hidden)]
1568pub struct _FROHFDIV;
1569#[doc = "`read()` method returns [frohfdiv::R](frohfdiv::R) reader structure"]
1570impl crate::Readable for FROHFDIV {}
1571#[doc = "`write(|w| ..)` method takes [frohfdiv::W](frohfdiv::W) writer structure"]
1572impl crate::Writable for FROHFDIV {}
1573#[doc = "FRO_HF (96MHz) clock divider"]
1574pub mod frohfdiv;
1575#[doc = "WDT clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdtclkdiv](wdtclkdiv) module"]
1576pub type WDTCLKDIV = crate::Reg<u32, _WDTCLKDIV>;
1577#[allow(missing_docs)]
1578#[doc(hidden)]
1579pub struct _WDTCLKDIV;
1580#[doc = "`read()` method returns [wdtclkdiv::R](wdtclkdiv::R) reader structure"]
1581impl crate::Readable for WDTCLKDIV {}
1582#[doc = "`write(|w| ..)` method takes [wdtclkdiv::W](wdtclkdiv::W) writer structure"]
1583impl crate::Writable for WDTCLKDIV {}
1584#[doc = "WDT clock divider"]
1585pub mod wdtclkdiv;
1586#[doc = "ADC clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcclkdiv](adcclkdiv) module"]
1587pub type ADCCLKDIV = crate::Reg<u32, _ADCCLKDIV>;
1588#[allow(missing_docs)]
1589#[doc(hidden)]
1590pub struct _ADCCLKDIV;
1591#[doc = "`read()` method returns [adcclkdiv::R](adcclkdiv::R) reader structure"]
1592impl crate::Readable for ADCCLKDIV {}
1593#[doc = "`write(|w| ..)` method takes [adcclkdiv::W](adcclkdiv::W) writer structure"]
1594impl crate::Writable for ADCCLKDIV {}
1595#[doc = "ADC clock divider"]
1596pub mod adcclkdiv;
1597#[doc = "USB0 Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clkdiv](usb0clkdiv) module"]
1598pub type USB0CLKDIV = crate::Reg<u32, _USB0CLKDIV>;
1599#[allow(missing_docs)]
1600#[doc(hidden)]
1601pub struct _USB0CLKDIV;
1602#[doc = "`read()` method returns [usb0clkdiv::R](usb0clkdiv::R) reader structure"]
1603impl crate::Readable for USB0CLKDIV {}
1604#[doc = "`write(|w| ..)` method takes [usb0clkdiv::W](usb0clkdiv::W) writer structure"]
1605impl crate::Writable for USB0CLKDIV {}
1606#[doc = "USB0 Clock divider"]
1607pub mod usb0clkdiv;
1608#[doc = "I2S MCLK clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkdiv](mclkdiv) module"]
1609pub type MCLKDIV = crate::Reg<u32, _MCLKDIV>;
1610#[allow(missing_docs)]
1611#[doc(hidden)]
1612pub struct _MCLKDIV;
1613#[doc = "`read()` method returns [mclkdiv::R](mclkdiv::R) reader structure"]
1614impl crate::Readable for MCLKDIV {}
1615#[doc = "`write(|w| ..)` method takes [mclkdiv::W](mclkdiv::W) writer structure"]
1616impl crate::Writable for MCLKDIV {}
1617#[doc = "I2S MCLK clock divider"]
1618pub mod mclkdiv;
1619#[doc = "SCT/PWM clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sctclkdiv](sctclkdiv) module"]
1620pub type SCTCLKDIV = crate::Reg<u32, _SCTCLKDIV>;
1621#[allow(missing_docs)]
1622#[doc(hidden)]
1623pub struct _SCTCLKDIV;
1624#[doc = "`read()` method returns [sctclkdiv::R](sctclkdiv::R) reader structure"]
1625impl crate::Readable for SCTCLKDIV {}
1626#[doc = "`write(|w| ..)` method takes [sctclkdiv::W](sctclkdiv::W) writer structure"]
1627impl crate::Writable for SCTCLKDIV {}
1628#[doc = "SCT/PWM clock divider"]
1629pub mod sctclkdiv;
1630#[doc = "SDIO clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclkdiv](sdioclkdiv) module"]
1631pub type SDIOCLKDIV = crate::Reg<u32, _SDIOCLKDIV>;
1632#[allow(missing_docs)]
1633#[doc(hidden)]
1634pub struct _SDIOCLKDIV;
1635#[doc = "`read()` method returns [sdioclkdiv::R](sdioclkdiv::R) reader structure"]
1636impl crate::Readable for SDIOCLKDIV {}
1637#[doc = "`write(|w| ..)` method takes [sdioclkdiv::W](sdioclkdiv::W) writer structure"]
1638impl crate::Writable for SDIOCLKDIV {}
1639#[doc = "SDIO clock divider"]
1640pub mod sdioclkdiv;
1641#[doc = "PLL0 clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0clkdiv](pll0clkdiv) module"]
1642pub type PLL0CLKDIV = crate::Reg<u32, _PLL0CLKDIV>;
1643#[allow(missing_docs)]
1644#[doc(hidden)]
1645pub struct _PLL0CLKDIV;
1646#[doc = "`read()` method returns [pll0clkdiv::R](pll0clkdiv::R) reader structure"]
1647impl crate::Readable for PLL0CLKDIV {}
1648#[doc = "`write(|w| ..)` method takes [pll0clkdiv::W](pll0clkdiv::W) writer structure"]
1649impl crate::Writable for PLL0CLKDIV {}
1650#[doc = "PLL0 clock divider"]
1651pub mod pll0clkdiv;
1652#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL)\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clockgenupdatelockout](clockgenupdatelockout) module"]
1653pub type CLOCKGENUPDATELOCKOUT = crate::Reg<u32, _CLOCKGENUPDATELOCKOUT>;
1654#[allow(missing_docs)]
1655#[doc(hidden)]
1656pub struct _CLOCKGENUPDATELOCKOUT;
1657#[doc = "`read()` method returns [clockgenupdatelockout::R](clockgenupdatelockout::R) reader structure"]
1658impl crate::Readable for CLOCKGENUPDATELOCKOUT {}
1659#[doc = "`write(|w| ..)` method takes [clockgenupdatelockout::W](clockgenupdatelockout::W) writer structure"]
1660impl crate::Writable for CLOCKGENUPDATELOCKOUT {}
1661#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL)"]
1662pub mod clockgenupdatelockout;
1663#[doc = "FMC configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmccr](fmccr) module"]
1664pub type FMCCR = crate::Reg<u32, _FMCCR>;
1665#[allow(missing_docs)]
1666#[doc(hidden)]
1667pub struct _FMCCR;
1668#[doc = "`read()` method returns [fmccr::R](fmccr::R) reader structure"]
1669impl crate::Readable for FMCCR {}
1670#[doc = "`write(|w| ..)` method takes [fmccr::W](fmccr::W) writer structure"]
1671impl crate::Writable for FMCCR {}
1672#[doc = "FMC configuration register"]
1673pub mod fmccr;
1674#[doc = "USB0 need clock control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0needclkctrl](usb0needclkctrl) module"]
1675pub type USB0NEEDCLKCTRL = crate::Reg<u32, _USB0NEEDCLKCTRL>;
1676#[allow(missing_docs)]
1677#[doc(hidden)]
1678pub struct _USB0NEEDCLKCTRL;
1679#[doc = "`read()` method returns [usb0needclkctrl::R](usb0needclkctrl::R) reader structure"]
1680impl crate::Readable for USB0NEEDCLKCTRL {}
1681#[doc = "`write(|w| ..)` method takes [usb0needclkctrl::W](usb0needclkctrl::W) writer structure"]
1682impl crate::Writable for USB0NEEDCLKCTRL {}
1683#[doc = "USB0 need clock control"]
1684pub mod usb0needclkctrl;
1685#[doc = "USB0 need clock status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0needclkstat](usb0needclkstat) module"]
1686pub type USB0NEEDCLKSTAT = crate::Reg<u32, _USB0NEEDCLKSTAT>;
1687#[allow(missing_docs)]
1688#[doc(hidden)]
1689pub struct _USB0NEEDCLKSTAT;
1690#[doc = "`read()` method returns [usb0needclkstat::R](usb0needclkstat::R) reader structure"]
1691impl crate::Readable for USB0NEEDCLKSTAT {}
1692#[doc = "`write(|w| ..)` method takes [usb0needclkstat::W](usb0needclkstat::W) writer structure"]
1693impl crate::Writable for USB0NEEDCLKSTAT {}
1694#[doc = "USB0 need clock status"]
1695pub mod usb0needclkstat;
1696#[doc = "FMCflush control\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmcflush](fmcflush) module"]
1697pub type FMCFLUSH = crate::Reg<u32, _FMCFLUSH>;
1698#[allow(missing_docs)]
1699#[doc(hidden)]
1700pub struct _FMCFLUSH;
1701#[doc = "`write(|w| ..)` method takes [fmcflush::W](fmcflush::W) writer structure"]
1702impl crate::Writable for FMCFLUSH {}
1703#[doc = "FMCflush control"]
1704pub mod fmcflush;
1705#[doc = "MCLK control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkio](mclkio) module"]
1706pub type MCLKIO = crate::Reg<u32, _MCLKIO>;
1707#[allow(missing_docs)]
1708#[doc(hidden)]
1709pub struct _MCLKIO;
1710#[doc = "`read()` method returns [mclkio::R](mclkio::R) reader structure"]
1711impl crate::Readable for MCLKIO {}
1712#[doc = "`write(|w| ..)` method takes [mclkio::W](mclkio::W) writer structure"]
1713impl crate::Writable for MCLKIO {}
1714#[doc = "MCLK control"]
1715pub mod mclkio;
1716#[doc = "USB1 need clock control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1needclkctrl](usb1needclkctrl) module"]
1717pub type USB1NEEDCLKCTRL = crate::Reg<u32, _USB1NEEDCLKCTRL>;
1718#[allow(missing_docs)]
1719#[doc(hidden)]
1720pub struct _USB1NEEDCLKCTRL;
1721#[doc = "`read()` method returns [usb1needclkctrl::R](usb1needclkctrl::R) reader structure"]
1722impl crate::Readable for USB1NEEDCLKCTRL {}
1723#[doc = "`write(|w| ..)` method takes [usb1needclkctrl::W](usb1needclkctrl::W) writer structure"]
1724impl crate::Writable for USB1NEEDCLKCTRL {}
1725#[doc = "USB1 need clock control"]
1726pub mod usb1needclkctrl;
1727#[doc = "USB1 need clock status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb1needclkstat](usb1needclkstat) module"]
1728pub type USB1NEEDCLKSTAT = crate::Reg<u32, _USB1NEEDCLKSTAT>;
1729#[allow(missing_docs)]
1730#[doc(hidden)]
1731pub struct _USB1NEEDCLKSTAT;
1732#[doc = "`read()` method returns [usb1needclkstat::R](usb1needclkstat::R) reader structure"]
1733impl crate::Readable for USB1NEEDCLKSTAT {}
1734#[doc = "`write(|w| ..)` method takes [usb1needclkstat::W](usb1needclkstat::W) writer structure"]
1735impl crate::Writable for USB1NEEDCLKSTAT {}
1736#[doc = "USB1 need clock status"]
1737pub mod usb1needclkstat;
1738#[doc = "SDIO CCLKIN phase and delay control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdioclkctrl](sdioclkctrl) module"]
1739pub type SDIOCLKCTRL = crate::Reg<u32, _SDIOCLKCTRL>;
1740#[allow(missing_docs)]
1741#[doc(hidden)]
1742pub struct _SDIOCLKCTRL;
1743#[doc = "`read()` method returns [sdioclkctrl::R](sdioclkctrl::R) reader structure"]
1744impl crate::Readable for SDIOCLKCTRL {}
1745#[doc = "`write(|w| ..)` method takes [sdioclkctrl::W](sdioclkctrl::W) writer structure"]
1746impl crate::Writable for SDIOCLKCTRL {}
1747#[doc = "SDIO CCLKIN phase and delay control"]
1748pub mod sdioclkctrl;
1749#[doc = "PLL1 550m control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1ctrl](pll1ctrl) module"]
1750pub type PLL1CTRL = crate::Reg<u32, _PLL1CTRL>;
1751#[allow(missing_docs)]
1752#[doc(hidden)]
1753pub struct _PLL1CTRL;
1754#[doc = "`read()` method returns [pll1ctrl::R](pll1ctrl::R) reader structure"]
1755impl crate::Readable for PLL1CTRL {}
1756#[doc = "`write(|w| ..)` method takes [pll1ctrl::W](pll1ctrl::W) writer structure"]
1757impl crate::Writable for PLL1CTRL {}
1758#[doc = "PLL1 550m control"]
1759pub mod pll1ctrl;
1760#[doc = "PLL1 550m status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1stat](pll1stat) module"]
1761pub type PLL1STAT = crate::Reg<u32, _PLL1STAT>;
1762#[allow(missing_docs)]
1763#[doc(hidden)]
1764pub struct _PLL1STAT;
1765#[doc = "`read()` method returns [pll1stat::R](pll1stat::R) reader structure"]
1766impl crate::Readable for PLL1STAT {}
1767#[doc = "`write(|w| ..)` method takes [pll1stat::W](pll1stat::W) writer structure"]
1768impl crate::Writable for PLL1STAT {}
1769#[doc = "PLL1 550m status"]
1770pub mod pll1stat;
1771#[doc = "PLL1 550m N divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1ndec](pll1ndec) module"]
1772pub type PLL1NDEC = crate::Reg<u32, _PLL1NDEC>;
1773#[allow(missing_docs)]
1774#[doc(hidden)]
1775pub struct _PLL1NDEC;
1776#[doc = "`read()` method returns [pll1ndec::R](pll1ndec::R) reader structure"]
1777impl crate::Readable for PLL1NDEC {}
1778#[doc = "`write(|w| ..)` method takes [pll1ndec::W](pll1ndec::W) writer structure"]
1779impl crate::Writable for PLL1NDEC {}
1780#[doc = "PLL1 550m N divider"]
1781pub mod pll1ndec;
1782#[doc = "PLL1 550m M divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1mdec](pll1mdec) module"]
1783pub type PLL1MDEC = crate::Reg<u32, _PLL1MDEC>;
1784#[allow(missing_docs)]
1785#[doc(hidden)]
1786pub struct _PLL1MDEC;
1787#[doc = "`read()` method returns [pll1mdec::R](pll1mdec::R) reader structure"]
1788impl crate::Readable for PLL1MDEC {}
1789#[doc = "`write(|w| ..)` method takes [pll1mdec::W](pll1mdec::W) writer structure"]
1790impl crate::Writable for PLL1MDEC {}
1791#[doc = "PLL1 550m M divider"]
1792pub mod pll1mdec;
1793#[doc = "PLL1 550m P divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1pdec](pll1pdec) module"]
1794pub type PLL1PDEC = crate::Reg<u32, _PLL1PDEC>;
1795#[allow(missing_docs)]
1796#[doc(hidden)]
1797pub struct _PLL1PDEC;
1798#[doc = "`read()` method returns [pll1pdec::R](pll1pdec::R) reader structure"]
1799impl crate::Readable for PLL1PDEC {}
1800#[doc = "`write(|w| ..)` method takes [pll1pdec::W](pll1pdec::W) writer structure"]
1801impl crate::Writable for PLL1PDEC {}
1802#[doc = "PLL1 550m P divider"]
1803pub mod pll1pdec;
1804#[doc = "PLL0 550m control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0ctrl](pll0ctrl) module"]
1805pub type PLL0CTRL = crate::Reg<u32, _PLL0CTRL>;
1806#[allow(missing_docs)]
1807#[doc(hidden)]
1808pub struct _PLL0CTRL;
1809#[doc = "`read()` method returns [pll0ctrl::R](pll0ctrl::R) reader structure"]
1810impl crate::Readable for PLL0CTRL {}
1811#[doc = "`write(|w| ..)` method takes [pll0ctrl::W](pll0ctrl::W) writer structure"]
1812impl crate::Writable for PLL0CTRL {}
1813#[doc = "PLL0 550m control"]
1814pub mod pll0ctrl;
1815#[doc = "PLL0 550m status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0stat](pll0stat) module"]
1816pub type PLL0STAT = crate::Reg<u32, _PLL0STAT>;
1817#[allow(missing_docs)]
1818#[doc(hidden)]
1819pub struct _PLL0STAT;
1820#[doc = "`read()` method returns [pll0stat::R](pll0stat::R) reader structure"]
1821impl crate::Readable for PLL0STAT {}
1822#[doc = "`write(|w| ..)` method takes [pll0stat::W](pll0stat::W) writer structure"]
1823impl crate::Writable for PLL0STAT {}
1824#[doc = "PLL0 550m status"]
1825pub mod pll0stat;
1826#[doc = "PLL0 550m N divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0ndec](pll0ndec) module"]
1827pub type PLL0NDEC = crate::Reg<u32, _PLL0NDEC>;
1828#[allow(missing_docs)]
1829#[doc(hidden)]
1830pub struct _PLL0NDEC;
1831#[doc = "`read()` method returns [pll0ndec::R](pll0ndec::R) reader structure"]
1832impl crate::Readable for PLL0NDEC {}
1833#[doc = "`write(|w| ..)` method takes [pll0ndec::W](pll0ndec::W) writer structure"]
1834impl crate::Writable for PLL0NDEC {}
1835#[doc = "PLL0 550m N divider"]
1836pub mod pll0ndec;
1837#[doc = "PLL0 550m P divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0pdec](pll0pdec) module"]
1838pub type PLL0PDEC = crate::Reg<u32, _PLL0PDEC>;
1839#[allow(missing_docs)]
1840#[doc(hidden)]
1841pub struct _PLL0PDEC;
1842#[doc = "`read()` method returns [pll0pdec::R](pll0pdec::R) reader structure"]
1843impl crate::Readable for PLL0PDEC {}
1844#[doc = "`write(|w| ..)` method takes [pll0pdec::W](pll0pdec::W) writer structure"]
1845impl crate::Writable for PLL0PDEC {}
1846#[doc = "PLL0 550m P divider"]
1847pub mod pll0pdec;
1848#[doc = "PLL0 Spread Spectrum Wrapper control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0sscg0](pll0sscg0) module"]
1849pub type PLL0SSCG0 = crate::Reg<u32, _PLL0SSCG0>;
1850#[allow(missing_docs)]
1851#[doc(hidden)]
1852pub struct _PLL0SSCG0;
1853#[doc = "`read()` method returns [pll0sscg0::R](pll0sscg0::R) reader structure"]
1854impl crate::Readable for PLL0SSCG0 {}
1855#[doc = "`write(|w| ..)` method takes [pll0sscg0::W](pll0sscg0::W) writer structure"]
1856impl crate::Writable for PLL0SSCG0 {}
1857#[doc = "PLL0 Spread Spectrum Wrapper control register 0"]
1858pub mod pll0sscg0;
1859#[doc = "PLL0 Spread Spectrum Wrapper control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll0sscg1](pll0sscg1) module"]
1860pub type PLL0SSCG1 = crate::Reg<u32, _PLL0SSCG1>;
1861#[allow(missing_docs)]
1862#[doc(hidden)]
1863pub struct _PLL0SSCG1;
1864#[doc = "`read()` method returns [pll0sscg1::R](pll0sscg1::R) reader structure"]
1865impl crate::Readable for PLL0SSCG1 {}
1866#[doc = "`write(|w| ..)` method takes [pll0sscg1::W](pll0sscg1::W) writer structure"]
1867impl crate::Writable for PLL0SSCG1 {}
1868#[doc = "PLL0 Spread Spectrum Wrapper control register 1"]
1869pub mod pll0sscg1;
1870#[doc = "CPU Control for multiple processors\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuctrl](cpuctrl) module"]
1871pub type CPUCTRL = crate::Reg<u32, _CPUCTRL>;
1872#[allow(missing_docs)]
1873#[doc(hidden)]
1874pub struct _CPUCTRL;
1875#[doc = "`read()` method returns [cpuctrl::R](cpuctrl::R) reader structure"]
1876impl crate::Readable for CPUCTRL {}
1877#[doc = "`write(|w| ..)` method takes [cpuctrl::W](cpuctrl::W) writer structure"]
1878impl crate::Writable for CPUCTRL {}
1879#[doc = "CPU Control for multiple processors"]
1880pub mod cpuctrl;
1881#[doc = "Coprocessor Boot Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpboot](cpboot) module"]
1882pub type CPBOOT = crate::Reg<u32, _CPBOOT>;
1883#[allow(missing_docs)]
1884#[doc(hidden)]
1885pub struct _CPBOOT;
1886#[doc = "`read()` method returns [cpboot::R](cpboot::R) reader structure"]
1887impl crate::Readable for CPBOOT {}
1888#[doc = "`write(|w| ..)` method takes [cpboot::W](cpboot::W) writer structure"]
1889impl crate::Writable for CPBOOT {}
1890#[doc = "Coprocessor Boot Address"]
1891pub mod cpboot;
1892#[doc = "CPU Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpstat](cpstat) module"]
1893pub type CPSTAT = crate::Reg<u32, _CPSTAT>;
1894#[allow(missing_docs)]
1895#[doc(hidden)]
1896pub struct _CPSTAT;
1897#[doc = "`read()` method returns [cpstat::R](cpstat::R) reader structure"]
1898impl crate::Readable for CPSTAT {}
1899#[doc = "`write(|w| ..)` method takes [cpstat::W](cpstat::W) writer structure"]
1900impl crate::Writable for CPSTAT {}
1901#[doc = "CPU Status"]
1902pub mod cpstat;
1903#[doc = "Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock_ctrl](clock_ctrl) module"]
1904pub type CLOCK_CTRL = crate::Reg<u32, _CLOCK_CTRL>;
1905#[allow(missing_docs)]
1906#[doc(hidden)]
1907pub struct _CLOCK_CTRL;
1908#[doc = "`read()` method returns [clock_ctrl::R](clock_ctrl::R) reader structure"]
1909impl crate::Readable for CLOCK_CTRL {}
1910#[doc = "`write(|w| ..)` method takes [clock_ctrl::W](clock_ctrl::W) writer structure"]
1911impl crate::Writable for CLOCK_CTRL {}
1912#[doc = "Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures"]
1913pub mod clock_ctrl;
1914#[doc = "Comparator Interrupt control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_int_ctrl](comp_int_ctrl) module"]
1915pub type COMP_INT_CTRL = crate::Reg<u32, _COMP_INT_CTRL>;
1916#[allow(missing_docs)]
1917#[doc(hidden)]
1918pub struct _COMP_INT_CTRL;
1919#[doc = "`read()` method returns [comp_int_ctrl::R](comp_int_ctrl::R) reader structure"]
1920impl crate::Readable for COMP_INT_CTRL {}
1921#[doc = "`write(|w| ..)` method takes [comp_int_ctrl::W](comp_int_ctrl::W) writer structure"]
1922impl crate::Writable for COMP_INT_CTRL {}
1923#[doc = "Comparator Interrupt control"]
1924pub mod comp_int_ctrl;
1925#[doc = "Comparator Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp_int_status](comp_int_status) module"]
1926pub type COMP_INT_STATUS = crate::Reg<u32, _COMP_INT_STATUS>;
1927#[allow(missing_docs)]
1928#[doc(hidden)]
1929pub struct _COMP_INT_STATUS;
1930#[doc = "`read()` method returns [comp_int_status::R](comp_int_status::R) reader structure"]
1931impl crate::Readable for COMP_INT_STATUS {}
1932#[doc = "`write(|w| ..)` method takes [comp_int_status::W](comp_int_status::W) writer structure"]
1933impl crate::Writable for COMP_INT_STATUS {}
1934#[doc = "Comparator Interrupt status"]
1935pub mod comp_int_status;
1936#[doc = "Control automatic clock gating\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [autoclkgateoverride](autoclkgateoverride) module"]
1937pub type AUTOCLKGATEOVERRIDE = crate::Reg<u32, _AUTOCLKGATEOVERRIDE>;
1938#[allow(missing_docs)]
1939#[doc(hidden)]
1940pub struct _AUTOCLKGATEOVERRIDE;
1941#[doc = "`read()` method returns [autoclkgateoverride::R](autoclkgateoverride::R) reader structure"]
1942impl crate::Readable for AUTOCLKGATEOVERRIDE {}
1943#[doc = "`write(|w| ..)` method takes [autoclkgateoverride::W](autoclkgateoverride::W) writer structure"]
1944impl crate::Writable for AUTOCLKGATEOVERRIDE {}
1945#[doc = "Control automatic clock gating"]
1946pub mod autoclkgateoverride;
1947#[doc = "Enable bypass of the first stage of synchonization inside GPIO_INT module\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpiopsync](gpiopsync) module"]
1948pub type GPIOPSYNC = crate::Reg<u32, _GPIOPSYNC>;
1949#[allow(missing_docs)]
1950#[doc(hidden)]
1951pub struct _GPIOPSYNC;
1952#[doc = "`read()` method returns [gpiopsync::R](gpiopsync::R) reader structure"]
1953impl crate::Readable for GPIOPSYNC {}
1954#[doc = "`write(|w| ..)` method takes [gpiopsync::W](gpiopsync::W) writer structure"]
1955impl crate::Writable for GPIOPSYNC {}
1956#[doc = "Enable bypass of the first stage of synchonization inside GPIO_INT module"]
1957pub mod gpiopsync;
1958#[doc = "Control write access to security registers.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_lock_en](debug_lock_en) module"]
1959pub type DEBUG_LOCK_EN = crate::Reg<u32, _DEBUG_LOCK_EN>;
1960#[allow(missing_docs)]
1961#[doc(hidden)]
1962pub struct _DEBUG_LOCK_EN;
1963#[doc = "`read()` method returns [debug_lock_en::R](debug_lock_en::R) reader structure"]
1964impl crate::Readable for DEBUG_LOCK_EN {}
1965#[doc = "`write(|w| ..)` method takes [debug_lock_en::W](debug_lock_en::W) writer structure"]
1966impl crate::Writable for DEBUG_LOCK_EN {}
1967#[doc = "Control write access to security registers."]
1968pub mod debug_lock_en;
1969#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_features](debug_features) module"]
1970pub type DEBUG_FEATURES = crate::Reg<u32, _DEBUG_FEATURES>;
1971#[allow(missing_docs)]
1972#[doc(hidden)]
1973pub struct _DEBUG_FEATURES;
1974#[doc = "`read()` method returns [debug_features::R](debug_features::R) reader structure"]
1975impl crate::Readable for DEBUG_FEATURES {}
1976#[doc = "`write(|w| ..)` method takes [debug_features::W](debug_features::W) writer structure"]
1977impl crate::Writable for DEBUG_FEATURES {}
1978#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control."]
1979pub mod debug_features;
1980#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_features_dp](debug_features_dp) module"]
1981pub type DEBUG_FEATURES_DP = crate::Reg<u32, _DEBUG_FEATURES_DP>;
1982#[allow(missing_docs)]
1983#[doc(hidden)]
1984pub struct _DEBUG_FEATURES_DP;
1985#[doc = "`read()` method returns [debug_features_dp::R](debug_features_dp::R) reader structure"]
1986impl crate::Readable for DEBUG_FEATURES_DP {}
1987#[doc = "`write(|w| ..)` method takes [debug_features_dp::W](debug_features_dp::W) writer structure"]
1988impl crate::Writable for DEBUG_FEATURES_DP {}
1989#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register."]
1990pub mod debug_features_dp;
1991#[doc = "block quiddikey/PUF all index.\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key_block](key_block) module"]
1992pub type KEY_BLOCK = crate::Reg<u32, _KEY_BLOCK>;
1993#[allow(missing_docs)]
1994#[doc(hidden)]
1995pub struct _KEY_BLOCK;
1996#[doc = "`write(|w| ..)` method takes [key_block::W](key_block::W) writer structure"]
1997impl crate::Writable for KEY_BLOCK {}
1998#[doc = "block quiddikey/PUF all index."]
1999pub mod key_block;
2000#[doc = "Debug authentication BEACON register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_auth_beacon](debug_auth_beacon) module"]
2001pub type DEBUG_AUTH_BEACON = crate::Reg<u32, _DEBUG_AUTH_BEACON>;
2002#[allow(missing_docs)]
2003#[doc(hidden)]
2004pub struct _DEBUG_AUTH_BEACON;
2005#[doc = "`read()` method returns [debug_auth_beacon::R](debug_auth_beacon::R) reader structure"]
2006impl crate::Readable for DEBUG_AUTH_BEACON {}
2007#[doc = "`write(|w| ..)` method takes [debug_auth_beacon::W](debug_auth_beacon::W) writer structure"]
2008impl crate::Writable for DEBUG_AUTH_BEACON {}
2009#[doc = "Debug authentication BEACON register"]
2010pub mod debug_auth_beacon;
2011#[doc = "CPUs configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpucfg](cpucfg) module"]
2012pub type CPUCFG = crate::Reg<u32, _CPUCFG>;
2013#[allow(missing_docs)]
2014#[doc(hidden)]
2015pub struct _CPUCFG;
2016#[doc = "`read()` method returns [cpucfg::R](cpucfg::R) reader structure"]
2017impl crate::Readable for CPUCFG {}
2018#[doc = "`write(|w| ..)` method takes [cpucfg::W](cpucfg::W) writer structure"]
2019impl crate::Writable for CPUCFG {}
2020#[doc = "CPUs configuration register"]
2021pub mod cpucfg;
2022#[doc = "Device ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [device_id0](device_id0) module"]
2023pub type DEVICE_ID0 = crate::Reg<u32, _DEVICE_ID0>;
2024#[allow(missing_docs)]
2025#[doc(hidden)]
2026pub struct _DEVICE_ID0;
2027#[doc = "`read()` method returns [device_id0::R](device_id0::R) reader structure"]
2028impl crate::Readable for DEVICE_ID0 {}
2029#[doc = "Device ID"]
2030pub mod device_id0;
2031#[doc = "Chip revision ID and Number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieid](dieid) module"]
2032pub type DIEID = crate::Reg<u32, _DIEID>;
2033#[allow(missing_docs)]
2034#[doc(hidden)]
2035pub struct _DIEID;
2036#[doc = "`read()` method returns [dieid::R](dieid::R) reader structure"]
2037impl crate::Readable for DIEID {}
2038#[doc = "Chip revision ID and Number"]
2039pub mod dieid;