lpc55s6x_pac/sct0/
capctrl5.rs

1#[doc = "Reader of register CAPCTRL5"]
2pub type R = crate::R<u32, super::CAPCTRL5>;
3#[doc = "Writer for register CAPCTRL5"]
4pub type W = crate::W<u32, super::CAPCTRL5>;
5#[doc = "Register CAPCTRL5 `reset()`'s with value 0"]
6impl crate::ResetValue for super::CAPCTRL5 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `CAPCONn_L`"]
14pub type CAPCONN_L_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `CAPCONn_L`"]
16pub struct CAPCONN_L_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> CAPCONN_L_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
24        self.w
25    }
26}
27#[doc = "Reader of field `CAPCONn_H`"]
28pub type CAPCONN_H_R = crate::R<u16, u16>;
29#[doc = "Write proxy for field `CAPCONn_H`"]
30pub struct CAPCONN_H_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> CAPCONN_H_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u16) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
38        self.w
39    }
40}
41impl R {
42    #[doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT."]
43    #[inline(always)]
44    pub fn capconn_l(&self) -> CAPCONN_L_R {
45        CAPCONN_L_R::new((self.bits & 0xffff) as u16)
46    }
47    #[doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT."]
48    #[inline(always)]
49    pub fn capconn_h(&self) -> CAPCONN_H_R {
50        CAPCONN_H_R::new(((self.bits >> 16) & 0xffff) as u16)
51    }
52}
53impl W {
54    #[doc = "Bits 0:15 - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of match/captures in this SCT."]
55    #[inline(always)]
56    pub fn capconn_l(&mut self) -> CAPCONN_L_W {
57        CAPCONN_L_W { w: self }
58    }
59    #[doc = "Bits 16:31 - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT."]
60    #[inline(always)]
61    pub fn capconn_h(&mut self) -> CAPCONN_H_W {
62        CAPCONN_H_W { w: self }
63    }
64}
lpc55s6x_pac/sct0/capctrl5.rs

lpc55s6x_pac/sct0/
capctrl5.rs
