[−][src]Enum lpc55s6x_pac::usart0::cfg::CLKPOL_A
Selects the clock polarity and sampling edge of received data in synchronous mode.
Value on reset: 0
Variants
0: Falling edge. Un_RXD is sampled on the falling edge of SCLK.
1: Rising edge. Un_RXD is sampled on the rising edge of SCLK.
Trait Implementations
impl Clone for CLKPOL_A
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fn clone(&self) -> CLKPOL_A
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fn clone_from(&mut self, source: &Self)
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impl Copy for CLKPOL_A
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impl Debug for CLKPOL_A
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impl From<CLKPOL_A> for bool
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impl PartialEq<CLKPOL_A> for CLKPOL_A
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impl StructuralPartialEq for CLKPOL_A
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Auto Trait Implementations
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,