Enum lpc55s6x_pac::syscon::sdioclkctrl::PHASE_ACTIVE_A

pub enum PHASE_ACTIVE_A {
    BYPASSED,
    PH_SHIFT,
}

Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.

Value on reset: 0

Variants

BYPASSED

0: Bypassed.

PH_SHIFT

1: Activates phase shift logic. When active, the clock divider is active and phase delays are enabled.

Trait Implementations

impl Clone for PHASE_ACTIVE_A

fn clone(&self) -> PHASE_ACTIVE_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PHASE_ACTIVE_A

impl Debug for PHASE_ACTIVE_A

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl From<PHASE_ACTIVE_A> for bool

fn from(variant: PHASE_ACTIVE_A) -> Self

Performs the conversion.

impl PartialEq<PHASE_ACTIVE_A> for PHASE_ACTIVE_A

fn eq(&self, other: &PHASE_ACTIVE_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use] fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for PHASE_ACTIVE_A