[−][src]Type Definition lpc55s6x_pac::syscon::pll1ctrl::R
type R = R<u32, PLL1CTRL>;
Reader of register PLL1CTRL
Methods
impl R[src]
pub fn selr(&self) -> SELR_R[src]
Bits 0:3 - Bandwidth select R value.
pub fn seli(&self) -> SELI_R[src]
Bits 4:9 - Bandwidth select I value.
pub fn selp(&self) -> SELP_R[src]
Bits 10:14 - Bandwidth select P value.
pub fn bypasspll(&self) -> BYPASSPLL_R[src]
Bit 15 - Bypass PLL input clock is sent directly to the PLL output (default).
pub fn bypasspostdiv2(&self) -> BYPASSPOSTDIV2_R[src]
Bit 16 - bypass of the divide-by-2 divider in the post-divider.
pub fn limupoff(&self) -> LIMUPOFF_R[src]
Bit 17 - limup_off = 1 in spread spectrum and fractional PLL applications.
pub fn bwdirect(&self) -> BWDIRECT_R[src]
Bit 18 - control of the bandwidth of the PLL.
pub fn bypassprediv(&self) -> BYPASSPREDIV_R[src]
Bit 19 - bypass of the pre-divider.
pub fn bypasspostdiv(&self) -> BYPASSPOSTDIV_R[src]
Bit 20 - bypass of the post-divider.
pub fn clken(&self) -> CLKEN_R[src]
Bit 21 - enable the output clock.
pub fn frmen(&self) -> FRMEN_R[src]
Bit 22 - 1: free running mode.
pub fn frmclkstable(&self) -> FRMCLKSTABLE_R[src]
Bit 23 - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable.
pub fn skewen(&self) -> SKEWEN_R[src]
Bit 24 - Skew mode.