Struct lpc55s6x_pac::ctimer0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ir: IR,
    pub tcr: TCR,
    pub tc: TC,
    pub pr: PR,
    pub pc: PC,
    pub mcr: MCR,
    pub mr: [MR; 4],
    pub ccr: CCR,
    pub cr: [CR; 4],
    pub emr: EMR,
    pub ctcr: CTCR,
    pub pwmc: PWMC,
    pub msr: [MSR; 4],
    // some fields omitted
}

Register block

Fields

ir: IR

0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

tcr: TCR

0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

tc: TC

0x08 - Timer Counter

pr: PR

0x0c - Prescale Register

pc: PC

0x10 - Prescale Counter

mcr: MCR

0x14 - Match Control Register

mr: [MR; 4]

0x18 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

ccr: CCR

0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

cr: [CR; 4]

0x2c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.

emr: EMR

0x3c - External Match Register. The EMR controls the match function and the external match pins.

ctcr: CTCR

0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

pwmc: PWMC

0x74 - PWM Control Register. This register enables PWM mode for the external match pins.

msr: [MSR; 4]

0x78 - Match Shadow Register