lpc55s6x_pac/hashcrypt/
ctrl.rs1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum MODE_A {
17 #[doc = "0: Disabled"]
18 DISABLED = 0,
19 #[doc = "1: SHA1 is enabled"]
20 SHA1 = 1,
21 #[doc = "2: SHA2-256 is enabled"]
22 SHA2_256 = 2,
23 #[doc = "4: AES if available (see also CRYPTCFG register for more controls)"]
24 AES = 4,
25 #[doc = "5: ICB-AES if available (see also CRYPTCFG register for more controls)"]
26 ICB_AES = 5,
27}
28impl From<MODE_A> for u8 {
29 #[inline(always)]
30 fn from(variant: MODE_A) -> Self {
31 variant as _
32 }
33}
34#[doc = "Reader of field `Mode`"]
35pub type MODE_R = crate::R<u8, MODE_A>;
36impl MODE_R {
37 #[doc = r"Get enumerated values variant"]
38 #[inline(always)]
39 pub fn variant(&self) -> crate::Variant<u8, MODE_A> {
40 use crate::Variant::*;
41 match self.bits {
42 0 => Val(MODE_A::DISABLED),
43 1 => Val(MODE_A::SHA1),
44 2 => Val(MODE_A::SHA2_256),
45 4 => Val(MODE_A::AES),
46 5 => Val(MODE_A::ICB_AES),
47 i => Res(i),
48 }
49 }
50 #[doc = "Checks if the value of the field is `DISABLED`"]
51 #[inline(always)]
52 pub fn is_disabled(&self) -> bool {
53 *self == MODE_A::DISABLED
54 }
55 #[doc = "Checks if the value of the field is `SHA1`"]
56 #[inline(always)]
57 pub fn is_sha1(&self) -> bool {
58 *self == MODE_A::SHA1
59 }
60 #[doc = "Checks if the value of the field is `SHA2_256`"]
61 #[inline(always)]
62 pub fn is_sha2_256(&self) -> bool {
63 *self == MODE_A::SHA2_256
64 }
65 #[doc = "Checks if the value of the field is `AES`"]
66 #[inline(always)]
67 pub fn is_aes(&self) -> bool {
68 *self == MODE_A::AES
69 }
70 #[doc = "Checks if the value of the field is `ICB_AES`"]
71 #[inline(always)]
72 pub fn is_icb_aes(&self) -> bool {
73 *self == MODE_A::ICB_AES
74 }
75}
76#[doc = "Write proxy for field `Mode`"]
77pub struct MODE_W<'a> {
78 w: &'a mut W,
79}
80impl<'a> MODE_W<'a> {
81 #[doc = r"Writes `variant` to the field"]
82 #[inline(always)]
83 pub fn variant(self, variant: MODE_A) -> &'a mut W {
84 unsafe { self.bits(variant.into()) }
85 }
86 #[doc = "Disabled"]
87 #[inline(always)]
88 pub fn disabled(self) -> &'a mut W {
89 self.variant(MODE_A::DISABLED)
90 }
91 #[doc = "SHA1 is enabled"]
92 #[inline(always)]
93 pub fn sha1(self) -> &'a mut W {
94 self.variant(MODE_A::SHA1)
95 }
96 #[doc = "SHA2-256 is enabled"]
97 #[inline(always)]
98 pub fn sha2_256(self) -> &'a mut W {
99 self.variant(MODE_A::SHA2_256)
100 }
101 #[doc = "AES if available (see also CRYPTCFG register for more controls)"]
102 #[inline(always)]
103 pub fn aes(self) -> &'a mut W {
104 self.variant(MODE_A::AES)
105 }
106 #[doc = "ICB-AES if available (see also CRYPTCFG register for more controls)"]
107 #[inline(always)]
108 pub fn icb_aes(self) -> &'a mut W {
109 self.variant(MODE_A::ICB_AES)
110 }
111 #[doc = r"Writes raw bits to the field"]
112 #[inline(always)]
113 pub unsafe fn bits(self, value: u8) -> &'a mut W {
114 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
115 self.w
116 }
117}
118#[doc = "Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq)]
120pub enum NEW_HASH_AW {
121 #[doc = "1: Starts a new Hash/Crypto and initializes the Digest/Result."]
122 START = 1,
123}
124impl From<NEW_HASH_AW> for bool {
125 #[inline(always)]
126 fn from(variant: NEW_HASH_AW) -> Self {
127 variant as u8 != 0
128 }
129}
130#[doc = "Write proxy for field `New_Hash`"]
131pub struct NEW_HASH_W<'a> {
132 w: &'a mut W,
133}
134impl<'a> NEW_HASH_W<'a> {
135 #[doc = r"Writes `variant` to the field"]
136 #[inline(always)]
137 pub fn variant(self, variant: NEW_HASH_AW) -> &'a mut W {
138 {
139 self.bit(variant.into())
140 }
141 }
142 #[doc = "Starts a new Hash/Crypto and initializes the Digest/Result."]
143 #[inline(always)]
144 pub fn start(self) -> &'a mut W {
145 self.variant(NEW_HASH_AW::START)
146 }
147 #[doc = r"Sets the field bit"]
148 #[inline(always)]
149 pub fn set_bit(self) -> &'a mut W {
150 self.bit(true)
151 }
152 #[doc = r"Clears the field bit"]
153 #[inline(always)]
154 pub fn clear_bit(self) -> &'a mut W {
155 self.bit(false)
156 }
157 #[doc = r"Writes raw bits to the field"]
158 #[inline(always)]
159 pub fn bit(self, value: bool) -> &'a mut W {
160 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
161 self.w
162 }
163}
164#[doc = "Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq)]
166pub enum DMA_I_A {
167 #[doc = "0: DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used."]
168 NOT_USED = 0,
169 #[doc = "1: DMA will push in the data."]
170 PUSH = 1,
171}
172impl From<DMA_I_A> for bool {
173 #[inline(always)]
174 fn from(variant: DMA_I_A) -> Self {
175 variant as u8 != 0
176 }
177}
178#[doc = "Reader of field `DMA_I`"]
179pub type DMA_I_R = crate::R<bool, DMA_I_A>;
180impl DMA_I_R {
181 #[doc = r"Get enumerated values variant"]
182 #[inline(always)]
183 pub fn variant(&self) -> DMA_I_A {
184 match self.bits {
185 false => DMA_I_A::NOT_USED,
186 true => DMA_I_A::PUSH,
187 }
188 }
189 #[doc = "Checks if the value of the field is `NOT_USED`"]
190 #[inline(always)]
191 pub fn is_not_used(&self) -> bool {
192 *self == DMA_I_A::NOT_USED
193 }
194 #[doc = "Checks if the value of the field is `PUSH`"]
195 #[inline(always)]
196 pub fn is_push(&self) -> bool {
197 *self == DMA_I_A::PUSH
198 }
199}
200#[doc = "Write proxy for field `DMA_I`"]
201pub struct DMA_I_W<'a> {
202 w: &'a mut W,
203}
204impl<'a> DMA_I_W<'a> {
205 #[doc = r"Writes `variant` to the field"]
206 #[inline(always)]
207 pub fn variant(self, variant: DMA_I_A) -> &'a mut W {
208 {
209 self.bit(variant.into())
210 }
211 }
212 #[doc = "DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used."]
213 #[inline(always)]
214 pub fn not_used(self) -> &'a mut W {
215 self.variant(DMA_I_A::NOT_USED)
216 }
217 #[doc = "DMA will push in the data."]
218 #[inline(always)]
219 pub fn push(self) -> &'a mut W {
220 self.variant(DMA_I_A::PUSH)
221 }
222 #[doc = r"Sets the field bit"]
223 #[inline(always)]
224 pub fn set_bit(self) -> &'a mut W {
225 self.bit(true)
226 }
227 #[doc = r"Clears the field bit"]
228 #[inline(always)]
229 pub fn clear_bit(self) -> &'a mut W {
230 self.bit(false)
231 }
232 #[doc = r"Writes raw bits to the field"]
233 #[inline(always)]
234 pub fn bit(self, value: bool) -> &'a mut W {
235 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
236 self.w
237 }
238}
239#[doc = "Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq)]
241pub enum DMA_O_A {
242 #[doc = "0: DMA is not used. Processor reads the digest/output in response to DIGEST interrupt."]
243 NOTUSED = 0,
244}
245impl From<DMA_O_A> for bool {
246 #[inline(always)]
247 fn from(variant: DMA_O_A) -> Self {
248 variant as u8 != 0
249 }
250}
251#[doc = "Reader of field `DMA_O`"]
252pub type DMA_O_R = crate::R<bool, DMA_O_A>;
253impl DMA_O_R {
254 #[doc = r"Get enumerated values variant"]
255 #[inline(always)]
256 pub fn variant(&self) -> crate::Variant<bool, DMA_O_A> {
257 use crate::Variant::*;
258 match self.bits {
259 false => Val(DMA_O_A::NOTUSED),
260 i => Res(i),
261 }
262 }
263 #[doc = "Checks if the value of the field is `NOTUSED`"]
264 #[inline(always)]
265 pub fn is_notused(&self) -> bool {
266 *self == DMA_O_A::NOTUSED
267 }
268}
269#[doc = "Write proxy for field `DMA_O`"]
270pub struct DMA_O_W<'a> {
271 w: &'a mut W,
272}
273impl<'a> DMA_O_W<'a> {
274 #[doc = r"Writes `variant` to the field"]
275 #[inline(always)]
276 pub fn variant(self, variant: DMA_O_A) -> &'a mut W {
277 {
278 self.bit(variant.into())
279 }
280 }
281 #[doc = "DMA is not used. Processor reads the digest/output in response to DIGEST interrupt."]
282 #[inline(always)]
283 pub fn notused(self) -> &'a mut W {
284 self.variant(DMA_O_A::NOTUSED)
285 }
286 #[doc = r"Sets the field bit"]
287 #[inline(always)]
288 pub fn set_bit(self) -> &'a mut W {
289 self.bit(true)
290 }
291 #[doc = r"Clears the field bit"]
292 #[inline(always)]
293 pub fn clear_bit(self) -> &'a mut W {
294 self.bit(false)
295 }
296 #[doc = r"Writes raw bits to the field"]
297 #[inline(always)]
298 pub fn bit(self, value: bool) -> &'a mut W {
299 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
300 self.w
301 }
302}
303#[doc = "Reader of field `HASHSWPB`"]
304pub type HASHSWPB_R = crate::R<bool, bool>;
305#[doc = "Write proxy for field `HASHSWPB`"]
306pub struct HASHSWPB_W<'a> {
307 w: &'a mut W,
308}
309impl<'a> HASHSWPB_W<'a> {
310 #[doc = r"Sets the field bit"]
311 #[inline(always)]
312 pub fn set_bit(self) -> &'a mut W {
313 self.bit(true)
314 }
315 #[doc = r"Clears the field bit"]
316 #[inline(always)]
317 pub fn clear_bit(self) -> &'a mut W {
318 self.bit(false)
319 }
320 #[doc = r"Writes raw bits to the field"]
321 #[inline(always)]
322 pub fn bit(self, value: bool) -> &'a mut W {
323 self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
324 self.w
325 }
326}
327impl R {
328 #[doc = "Bits 0:2 - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
329 #[inline(always)]
330 pub fn mode(&self) -> MODE_R {
331 MODE_R::new((self.bits & 0x07) as u8)
332 }
333 #[doc = "Bit 8 - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
334 #[inline(always)]
335 pub fn dma_i(&self) -> DMA_I_R {
336 DMA_I_R::new(((self.bits >> 8) & 0x01) != 0)
337 }
338 #[doc = "Bit 9 - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
339 #[inline(always)]
340 pub fn dma_o(&self) -> DMA_O_R {
341 DMA_O_R::new(((self.bits >> 9) & 0x01) != 0)
342 }
343 #[doc = "Bit 12 - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
344 #[inline(always)]
345 pub fn hashswpb(&self) -> HASHSWPB_R {
346 HASHSWPB_R::new(((self.bits >> 12) & 0x01) != 0)
347 }
348}
349impl W {
350 #[doc = "Bits 0:2 - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
351 #[inline(always)]
352 pub fn mode(&mut self) -> MODE_W {
353 MODE_W { w: self }
354 }
355 #[doc = "Bit 4 - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1."]
356 #[inline(always)]
357 pub fn new_hash(&mut self) -> NEW_HASH_W {
358 NEW_HASH_W { w: self }
359 }
360 #[doc = "Bit 8 - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
361 #[inline(always)]
362 pub fn dma_i(&mut self) -> DMA_I_W {
363 DMA_I_W { w: self }
364 }
365 #[doc = "Bit 9 - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
366 #[inline(always)]
367 pub fn dma_o(&mut self) -> DMA_O_W {
368 DMA_O_W { w: self }
369 }
370 #[doc = "Bit 12 - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
371 #[inline(always)]
372 pub fn hashswpb(&mut self) -> HASHSWPB_W {
373 HASHSWPB_W { w: self }
374 }
375}