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#[doc = "Reader of register INTB0"] pub type R = crate::R<u32, super::INTB0>; #[doc = "Writer for register INTB0"] pub type W = crate::W<u32, super::INTB0>; #[doc = "Register INTB0 `reset()`'s with value 0"] impl crate::ResetValue for super::INTB0 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `IB`"] pub type IB_R = crate::R<u32, u32>; #[doc = "Write proxy for field `IB`"] pub struct IB_W<'a> { w: &'a mut W, } impl<'a> IB_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff); self.w } } impl R { #[doc = "Bits 0:31 - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."] #[inline(always)] pub fn ib(&self) -> IB_R { IB_R::new((self.bits & 0xffff_ffff) as u32) } } impl W { #[doc = "Bits 0:31 - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel interrupt B is not active. 1 = the DMA channel interrupt B is active."] #[inline(always)] pub fn ib(&mut self) -> IB_W { IB_W { w: self } } }