Struct lpc55s6x_pac::sct0::config::CLKMODE_W

pub struct CLKMODE_W<'a> { /* fields omitted */ }

Write proxy for field CLKMODE

Methods

impl<'a> CLKMODE_W<'a>

pub fn variant(self, variant: CLKMODE_A) -> &'a mut W

Writes variant to the field

pub fn system_clock_mode(self) -> &'a mut W

System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.

pub fn sampled_system_clock_mode(self) -> &'a mut W

Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.

pub fn sct_input_clock_mode(self) -> &'a mut W

SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.

pub fn asynchronous_mode(self) -> &'a mut W

Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.

pub fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field