1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
#[doc = "Reader of register UTMIPLUS_ULPI_DEBUG"] pub type R = crate::R<u32, super::UTMIPLUS_ULPI_DEBUG>; #[doc = "Writer for register UTMIPLUS_ULPI_DEBUG"] pub type W = crate::W<u32, super::UTMIPLUS_ULPI_DEBUG>; #[doc = "Register UTMIPLUS_ULPI_DEBUG `reset()`'s with value 0"] impl crate::ResetValue for super::UTMIPLUS_ULPI_DEBUG { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `PHY_ADDR`"] pub type PHY_ADDR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PHY_ADDR`"] pub struct PHY_ADDR_W<'a> { w: &'a mut W, } impl<'a> PHY_ADDR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff); self.w } } #[doc = "Reader of field `PHY_WDATA`"] pub type PHY_WDATA_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PHY_WDATA`"] pub struct PHY_WDATA_W<'a> { w: &'a mut W, } impl<'a> PHY_WDATA_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8); self.w } } #[doc = "Reader of field `PHY_RDATA`"] pub type PHY_RDATA_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PHY_RDATA`"] pub struct PHY_RDATA_W<'a> { w: &'a mut W, } impl<'a> PHY_RDATA_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); self.w } } #[doc = "Reader of field `PHY_RW`"] pub type PHY_RW_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PHY_RW`"] pub struct PHY_RW_W<'a> { w: &'a mut W, } impl<'a> PHY_RW_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `PHY_ACCESS`"] pub type PHY_ACCESS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PHY_ACCESS`"] pub struct PHY_ACCESS_W<'a> { w: &'a mut W, } impl<'a> PHY_ACCESS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); self.w } } #[doc = "Reader of field `PHY_MODE`"] pub type PHY_MODE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PHY_MODE`"] pub struct PHY_MODE_W<'a> { w: &'a mut W, } impl<'a> PHY_MODE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:7 - UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."] #[inline(always)] pub fn phy_addr(&self) -> PHY_ADDR_R { PHY_ADDR_R::new((self.bits & 0xff) as u8) } #[doc = "Bits 8:15 - UTMI+ mode: Reserved."] #[inline(always)] pub fn phy_wdata(&self) -> PHY_WDATA_R { PHY_WDATA_R::new(((self.bits >> 8) & 0xff) as u8) } #[doc = "Bits 16:23 - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."] #[inline(always)] pub fn phy_rdata(&self) -> PHY_RDATA_R { PHY_RDATA_R::new(((self.bits >> 16) & 0xff) as u8) } #[doc = "Bit 24 - UTMI+ mode: Reserved."] #[inline(always)] pub fn phy_rw(&self) -> PHY_RW_R { PHY_RW_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bit 25 - Software writes this bit to one to start a read or write operation."] #[inline(always)] pub fn phy_access(&self) -> PHY_ACCESS_R { PHY_ACCESS_R::new(((self.bits >> 25) & 0x01) != 0) } #[doc = "Bit 31 - This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW."] #[inline(always)] pub fn phy_mode(&self) -> PHY_MODE_R { PHY_MODE_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:7 - UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface."] #[inline(always)] pub fn phy_addr(&mut self) -> PHY_ADDR_W { PHY_ADDR_W { w: self } } #[doc = "Bits 8:15 - UTMI+ mode: Reserved."] #[inline(always)] pub fn phy_wdata(&mut self) -> PHY_WDATA_W { PHY_WDATA_W { w: self } } #[doc = "Bits 16:23 - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register."] #[inline(always)] pub fn phy_rdata(&mut self) -> PHY_RDATA_W { PHY_RDATA_W { w: self } } #[doc = "Bit 24 - UTMI+ mode: Reserved."] #[inline(always)] pub fn phy_rw(&mut self) -> PHY_RW_W { PHY_RW_W { w: self } } #[doc = "Bit 25 - Software writes this bit to one to start a read or write operation."] #[inline(always)] pub fn phy_access(&mut self) -> PHY_ACCESS_W { PHY_ACCESS_W { w: self } } #[doc = "Bit 31 - This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW."] #[inline(always)] pub fn phy_mode(&mut self) -> PHY_MODE_W { PHY_MODE_W { w: self } } }