Type Definition lpc55s6x_pac::spi0::fifocfg::R

type R = R<u32, FIFOCFG>;

Reader of register FIFOCFG

Methods

impl R

pub fn enabletx(&self) -> ENABLETX_R

Bit 0 - Enable the transmit FIFO.

pub fn enablerx(&self) -> ENABLERX_R

Bit 1 - Enable the receive FIFO.

pub fn size(&self) -> SIZE_R

Bits 4:5 - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.

pub fn dmatx(&self) -> DMATX_R

Bit 12 - DMA configuration for transmit.

pub fn dmarx(&self) -> DMARX_R

Bit 13 - DMA configuration for receive.

pub fn waketx(&self) -> WAKETX_R

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn wakerx(&self) -> WAKERX_R

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn emptytx(&self) -> EMPTYTX_R

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

pub fn emptyrx(&self) -> EMPTYRX_R

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

pub fn popdbg(&self) -> POPDBG_R

Bit 18 - Pop FIFO for debug reads.