Type Definition lpc55s6x_pac::pmc::resetcause::R

type R = R<u32, RESETCAUSE>;

Reader of register RESETCAUSE

Methods

impl R

pub fn por(&self) -> POR_R

Bit 0 - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit.

pub fn padreset(&self) -> PADRESET_R

Bit 1 - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit.

pub fn bodreset(&self) -> BODRESET_R

Bit 2 - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit.

pub fn systemreset(&self) -> SYSTEMRESET_R

Bit 3 - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit.

pub fn wdtreset(&self) -> WDTRESET_R

Bit 4 - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit.

pub fn swrreset(&self) -> SWRRESET_R

Bit 5 - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit.

pub fn dpdreset_wakeupio(&self) -> DPDRESET_WAKEUPIO_R

Bit 6 - 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit.

pub fn dpdreset_rtc(&self) -> DPDRESET_RTC_R

Bit 7 - 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit.

pub fn dpdreset_ostimer(&self) -> DPDRESET_OSTIMER_R

Bit 8 - 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit.