lpc550x/syscon/
pll1stat.rs

1#[doc = "Register `PLL1STAT` reader"]
2pub struct R(crate::R<PLL1STAT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLL1STAT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLL1STAT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLL1STAT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLL1STAT` writer"]
17pub struct W(crate::W<PLL1STAT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLL1STAT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLL1STAT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLL1STAT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `LOCK` reader - lock detector output (active high) Warning: The lock signal is only reliable between fref\\[2\\]
38:100 kHz to 20 MHz."]
39pub type LOCK_R = crate::BitReader<bool>;
40#[doc = "Field `PREDIVACK` reader - pre-divider ratio change acknowledge."]
41pub type PREDIVACK_R = crate::BitReader<bool>;
42#[doc = "Field `FEEDDIVACK` reader - feedback divider ratio change acknowledge."]
43pub type FEEDDIVACK_R = crate::BitReader<bool>;
44#[doc = "Field `POSTDIVACK` reader - post-divider ratio change acknowledge."]
45pub type POSTDIVACK_R = crate::BitReader<bool>;
46#[doc = "Field `FRMDET` reader - free running detector output (active high)."]
47pub type FRMDET_R = crate::BitReader<bool>;
48impl R {
49    #[doc = "Bit 0 - lock detector output (active high) Warning: The lock signal is only reliable between fref\\[2\\]
50:100 kHz to 20 MHz."]
51    #[inline(always)]
52    pub fn lock(&self) -> LOCK_R {
53        LOCK_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - pre-divider ratio change acknowledge."]
56    #[inline(always)]
57    pub fn predivack(&self) -> PREDIVACK_R {
58        PREDIVACK_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - feedback divider ratio change acknowledge."]
61    #[inline(always)]
62    pub fn feeddivack(&self) -> FEEDDIVACK_R {
63        FEEDDIVACK_R::new(((self.bits >> 2) & 1) != 0)
64    }
65    #[doc = "Bit 3 - post-divider ratio change acknowledge."]
66    #[inline(always)]
67    pub fn postdivack(&self) -> POSTDIVACK_R {
68        POSTDIVACK_R::new(((self.bits >> 3) & 1) != 0)
69    }
70    #[doc = "Bit 4 - free running detector output (active high)."]
71    #[inline(always)]
72    pub fn frmdet(&self) -> FRMDET_R {
73        FRMDET_R::new(((self.bits >> 4) & 1) != 0)
74    }
75}
76impl W {
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "PLL1 550m status.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1stat](index.html) module"]
85pub struct PLL1STAT_SPEC;
86impl crate::RegisterSpec for PLL1STAT_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [pll1stat::R](R) reader structure"]
90impl crate::Readable for PLL1STAT_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [pll1stat::W](W) writer structure"]
94impl crate::Writable for PLL1STAT_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets PLL1STAT to value 0"]
98impl crate::Resettable for PLL1STAT_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
lpc550x/syscon/pll1stat.rs

lpc550x/syscon/
pll1stat.rs
