lpc550x/mrt0/channel/
intval.rs

1#[doc = "Register `INTVAL` reader"]
2pub struct R(crate::R<INTVAL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTVAL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTVAL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTVAL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTVAL` writer"]
17pub struct W(crate::W<INTVAL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTVAL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTVAL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTVAL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IVALUE` reader - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval."]
38pub type IVALUE_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `IVALUE` writer - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval."]
40pub type IVALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, INTVAL_SPEC, u32, u32, 24, O>;
41#[doc = "Field `LOAD` reader - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0."]
42pub type LOAD_R = crate::BitReader<LOAD_A>;
43#[doc = "Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum LOAD_A {
46    #[doc = "0: No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected."]
47    NO_FORCE_LOAD = 0,
48    #[doc = "1: Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running."]
49    FORCE_LOAD = 1,
50}
51impl From<LOAD_A> for bool {
52    #[inline(always)]
53    fn from(variant: LOAD_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl LOAD_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> LOAD_A {
61        match self.bits {
62            false => LOAD_A::NO_FORCE_LOAD,
63            true => LOAD_A::FORCE_LOAD,
64        }
65    }
66    #[doc = "Checks if the value of the field is `NO_FORCE_LOAD`"]
67    #[inline(always)]
68    pub fn is_no_force_load(&self) -> bool {
69        *self == LOAD_A::NO_FORCE_LOAD
70    }
71    #[doc = "Checks if the value of the field is `FORCE_LOAD`"]
72    #[inline(always)]
73    pub fn is_force_load(&self) -> bool {
74        *self == LOAD_A::FORCE_LOAD
75    }
76}
77#[doc = "Field `LOAD` writer - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0."]
78pub type LOAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTVAL_SPEC, LOAD_A, O>;
79impl<'a, const O: u8> LOAD_W<'a, O> {
80    #[doc = "No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected."]
81    #[inline(always)]
82    pub fn no_force_load(self) -> &'a mut W {
83        self.variant(LOAD_A::NO_FORCE_LOAD)
84    }
85    #[doc = "Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running."]
86    #[inline(always)]
87    pub fn force_load(self) -> &'a mut W {
88        self.variant(LOAD_A::FORCE_LOAD)
89    }
90}
91impl R {
92    #[doc = "Bits 0:23 - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval."]
93    #[inline(always)]
94    pub fn ivalue(&self) -> IVALUE_R {
95        IVALUE_R::new((self.bits & 0x00ff_ffff) as u32)
96    }
97    #[doc = "Bit 31 - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0."]
98    #[inline(always)]
99    pub fn load(&self) -> LOAD_R {
100        LOAD_R::new(((self.bits >> 31) & 1) != 0)
101    }
102}
103impl W {
104    #[doc = "Bits 0:23 - Time interval load value. This value is loaded into the TIMERn register and the MRT channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to this bit field starts the timer immediately. If the timer is running, writing a zero to this bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer stops at the end of the time interval."]
105    #[inline(always)]
106    pub fn ivalue(&mut self) -> IVALUE_W<0> {
107        IVALUE_W::new(self)
108    }
109    #[doc = "Bit 31 - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0."]
110    #[inline(always)]
111    pub fn load(&mut self) -> LOAD_W<31> {
112        LOAD_W::new(self)
113    }
114    #[doc = "Writes raw bits to the register."]
115    #[inline(always)]
116    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
117        self.0.bits(bits);
118        self
119    }
120}
121#[doc = "MRT Time interval value register. This value is loaded into the TIMER register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intval](index.html) module"]
122pub struct INTVAL_SPEC;
123impl crate::RegisterSpec for INTVAL_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [intval::R](R) reader structure"]
127impl crate::Readable for INTVAL_SPEC {
128    type Reader = R;
129}
130#[doc = "`write(|w| ..)` method takes [intval::W](W) writer structure"]
131impl crate::Writable for INTVAL_SPEC {
132    type Writer = W;
133}
134#[doc = "`reset()` method sets INTVAL to value 0"]
135impl crate::Resettable for INTVAL_SPEC {
136    #[inline(always)]
137    fn reset_value() -> Self::Ux {
138        0
139    }
140}
lpc550x/mrt0/channel/intval.rs

lpc550x/mrt0/channel/
intval.rs
