lpc550x/i2c0/
intenclr.rs

1#[doc = "Register `INTENCLR` writer"]
2pub struct W(crate::W<INTENCLR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<INTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<INTENCLR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `MSTPENDINGCLR` writer - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented."]
23pub type MSTPENDINGCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
24#[doc = "Field `MSTARBLOSSCLR` writer - Master Arbitration Loss interrupt clear."]
25pub type MSTARBLOSSCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
26#[doc = "Field `MSTSTSTPERRCLR` writer - Master Start/Stop Error interrupt clear."]
27pub type MSTSTSTPERRCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
28#[doc = "Field `SLVPENDINGCLR` writer - Slave Pending interrupt clear."]
29pub type SLVPENDINGCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
30#[doc = "Field `SLVNOTSTRCLR` writer - Slave Not Stretching interrupt clear."]
31pub type SLVNOTSTRCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
32#[doc = "Field `SLVDESELCLR` writer - Slave Deselect interrupt clear."]
33pub type SLVDESELCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
34#[doc = "Field `MONRDYCLR` writer - Monitor data Ready interrupt clear."]
35pub type MONRDYCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
36#[doc = "Field `MONOVCLR` writer - Monitor Overrun interrupt clear."]
37pub type MONOVCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
38#[doc = "Field `MONIDLECLR` writer - Monitor Idle interrupt clear."]
39pub type MONIDLECLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
40#[doc = "Field `EVENTTIMEOUTCLR` writer - Event time-out interrupt clear."]
41pub type EVENTTIMEOUTCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
42#[doc = "Field `SCLTIMEOUTCLR` writer - SCL time-out interrupt clear."]
43pub type SCLTIMEOUTCLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
44impl W {
45    #[doc = "Bit 0 - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented."]
46    #[inline(always)]
47    pub fn mstpendingclr(&mut self) -> MSTPENDINGCLR_W<0> {
48        MSTPENDINGCLR_W::new(self)
49    }
50    #[doc = "Bit 4 - Master Arbitration Loss interrupt clear."]
51    #[inline(always)]
52    pub fn mstarblossclr(&mut self) -> MSTARBLOSSCLR_W<4> {
53        MSTARBLOSSCLR_W::new(self)
54    }
55    #[doc = "Bit 6 - Master Start/Stop Error interrupt clear."]
56    #[inline(always)]
57    pub fn mstststperrclr(&mut self) -> MSTSTSTPERRCLR_W<6> {
58        MSTSTSTPERRCLR_W::new(self)
59    }
60    #[doc = "Bit 8 - Slave Pending interrupt clear."]
61    #[inline(always)]
62    pub fn slvpendingclr(&mut self) -> SLVPENDINGCLR_W<8> {
63        SLVPENDINGCLR_W::new(self)
64    }
65    #[doc = "Bit 11 - Slave Not Stretching interrupt clear."]
66    #[inline(always)]
67    pub fn slvnotstrclr(&mut self) -> SLVNOTSTRCLR_W<11> {
68        SLVNOTSTRCLR_W::new(self)
69    }
70    #[doc = "Bit 15 - Slave Deselect interrupt clear."]
71    #[inline(always)]
72    pub fn slvdeselclr(&mut self) -> SLVDESELCLR_W<15> {
73        SLVDESELCLR_W::new(self)
74    }
75    #[doc = "Bit 16 - Monitor data Ready interrupt clear."]
76    #[inline(always)]
77    pub fn monrdyclr(&mut self) -> MONRDYCLR_W<16> {
78        MONRDYCLR_W::new(self)
79    }
80    #[doc = "Bit 17 - Monitor Overrun interrupt clear."]
81    #[inline(always)]
82    pub fn monovclr(&mut self) -> MONOVCLR_W<17> {
83        MONOVCLR_W::new(self)
84    }
85    #[doc = "Bit 19 - Monitor Idle interrupt clear."]
86    #[inline(always)]
87    pub fn monidleclr(&mut self) -> MONIDLECLR_W<19> {
88        MONIDLECLR_W::new(self)
89    }
90    #[doc = "Bit 24 - Event time-out interrupt clear."]
91    #[inline(always)]
92    pub fn eventtimeoutclr(&mut self) -> EVENTTIMEOUTCLR_W<24> {
93        EVENTTIMEOUTCLR_W::new(self)
94    }
95    #[doc = "Bit 25 - SCL time-out interrupt clear."]
96    #[inline(always)]
97    pub fn scltimeoutclr(&mut self) -> SCLTIMEOUTCLR_W<25> {
98        SCLTIMEOUTCLR_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Interrupt Enable Clear register.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
108pub struct INTENCLR_SPEC;
109impl crate::RegisterSpec for INTENCLR_SPEC {
110    type Ux = u32;
111}
112#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
113impl crate::Writable for INTENCLR_SPEC {
114    type Writer = W;
115}
116#[doc = "`reset()` method sets INTENCLR to value 0"]
117impl crate::Resettable for INTENCLR_SPEC {
118    #[inline(always)]
119    fn reset_value() -> Self::Ux {
120        0
121    }
122}
lpc550x/i2c0/intenclr.rs

lpc550x/i2c0/
intenclr.rs
