lpc55_pac/usart0/
cfg.rs

1#[doc = "Register `CFG` reader"]
2pub struct R(crate::R<CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG` writer"]
17pub struct W(crate::W<CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "USART Enable.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum ENABLE_A {
40    #[doc = "0: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
41    DISABLED = 0,
42    #[doc = "1: Enabled. The USART is enabled for operation."]
43    ENABLED = 1,
44}
45impl From<ENABLE_A> for bool {
46    #[inline(always)]
47    fn from(variant: ENABLE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `ENABLE` reader - USART Enable."]
52pub struct ENABLE_R(crate::FieldReader<bool, ENABLE_A>);
53impl ENABLE_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        ENABLE_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> ENABLE_A {
61        match self.bits {
62            false => ENABLE_A::DISABLED,
63            true => ENABLE_A::ENABLED,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DISABLED`"]
67    #[inline(always)]
68    pub fn is_disabled(&self) -> bool {
69        **self == ENABLE_A::DISABLED
70    }
71    #[doc = "Checks if the value of the field is `ENABLED`"]
72    #[inline(always)]
73    pub fn is_enabled(&self) -> bool {
74        **self == ENABLE_A::ENABLED
75    }
76}
77impl core::ops::Deref for ENABLE_R {
78    type Target = crate::FieldReader<bool, ENABLE_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `ENABLE` writer - USART Enable."]
85pub struct ENABLE_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> ENABLE_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: ENABLE_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
95    #[inline(always)]
96    pub fn disabled(self) -> &'a mut W {
97        self.variant(ENABLE_A::DISABLED)
98    }
99    #[doc = "Enabled. The USART is enabled for operation."]
100    #[inline(always)]
101    pub fn enabled(self) -> &'a mut W {
102        self.variant(ENABLE_A::ENABLED)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Selects the data size for the USART.\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123#[repr(u8)]
124pub enum DATALEN_A {
125    #[doc = "0: 7 bit Data length."]
126    BIT_7 = 0,
127    #[doc = "1: 8 bit Data length."]
128    BIT_8 = 1,
129    #[doc = "2: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
130    BIT_9 = 2,
131}
132impl From<DATALEN_A> for u8 {
133    #[inline(always)]
134    fn from(variant: DATALEN_A) -> Self {
135        variant as _
136    }
137}
138#[doc = "Field `DATALEN` reader - Selects the data size for the USART."]
139pub struct DATALEN_R(crate::FieldReader<u8, DATALEN_A>);
140impl DATALEN_R {
141    #[inline(always)]
142    pub(crate) fn new(bits: u8) -> Self {
143        DATALEN_R(crate::FieldReader::new(bits))
144    }
145    #[doc = r"Get enumerated values variant"]
146    #[inline(always)]
147    pub fn variant(&self) -> Option<DATALEN_A> {
148        match self.bits {
149            0 => Some(DATALEN_A::BIT_7),
150            1 => Some(DATALEN_A::BIT_8),
151            2 => Some(DATALEN_A::BIT_9),
152            _ => None,
153        }
154    }
155    #[doc = "Checks if the value of the field is `BIT_7`"]
156    #[inline(always)]
157    pub fn is_bit_7(&self) -> bool {
158        **self == DATALEN_A::BIT_7
159    }
160    #[doc = "Checks if the value of the field is `BIT_8`"]
161    #[inline(always)]
162    pub fn is_bit_8(&self) -> bool {
163        **self == DATALEN_A::BIT_8
164    }
165    #[doc = "Checks if the value of the field is `BIT_9`"]
166    #[inline(always)]
167    pub fn is_bit_9(&self) -> bool {
168        **self == DATALEN_A::BIT_9
169    }
170}
171impl core::ops::Deref for DATALEN_R {
172    type Target = crate::FieldReader<u8, DATALEN_A>;
173    #[inline(always)]
174    fn deref(&self) -> &Self::Target {
175        &self.0
176    }
177}
178#[doc = "Field `DATALEN` writer - Selects the data size for the USART."]
179pub struct DATALEN_W<'a> {
180    w: &'a mut W,
181}
182impl<'a> DATALEN_W<'a> {
183    #[doc = r"Writes `variant` to the field"]
184    #[inline(always)]
185    pub fn variant(self, variant: DATALEN_A) -> &'a mut W {
186        unsafe { self.bits(variant.into()) }
187    }
188    #[doc = "7 bit Data length."]
189    #[inline(always)]
190    pub fn bit_7(self) -> &'a mut W {
191        self.variant(DATALEN_A::BIT_7)
192    }
193    #[doc = "8 bit Data length."]
194    #[inline(always)]
195    pub fn bit_8(self) -> &'a mut W {
196        self.variant(DATALEN_A::BIT_8)
197    }
198    #[doc = "9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
199    #[inline(always)]
200    pub fn bit_9(self) -> &'a mut W {
201        self.variant(DATALEN_A::BIT_9)
202    }
203    #[doc = r"Writes raw bits to the field"]
204    #[inline(always)]
205    pub unsafe fn bits(self, value: u8) -> &'a mut W {
206        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
207        self.w
208    }
209}
210#[doc = "Selects what type of parity is used by the USART.\n\nValue on reset: 0"]
211#[derive(Clone, Copy, Debug, PartialEq)]
212#[repr(u8)]
213pub enum PARITYSEL_A {
214    #[doc = "0: No parity."]
215    NO_PARITY = 0,
216    #[doc = "2: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
217    EVEN_PARITY = 2,
218    #[doc = "3: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
219    ODD_PARITY = 3,
220}
221impl From<PARITYSEL_A> for u8 {
222    #[inline(always)]
223    fn from(variant: PARITYSEL_A) -> Self {
224        variant as _
225    }
226}
227#[doc = "Field `PARITYSEL` reader - Selects what type of parity is used by the USART."]
228pub struct PARITYSEL_R(crate::FieldReader<u8, PARITYSEL_A>);
229impl PARITYSEL_R {
230    #[inline(always)]
231    pub(crate) fn new(bits: u8) -> Self {
232        PARITYSEL_R(crate::FieldReader::new(bits))
233    }
234    #[doc = r"Get enumerated values variant"]
235    #[inline(always)]
236    pub fn variant(&self) -> Option<PARITYSEL_A> {
237        match self.bits {
238            0 => Some(PARITYSEL_A::NO_PARITY),
239            2 => Some(PARITYSEL_A::EVEN_PARITY),
240            3 => Some(PARITYSEL_A::ODD_PARITY),
241            _ => None,
242        }
243    }
244    #[doc = "Checks if the value of the field is `NO_PARITY`"]
245    #[inline(always)]
246    pub fn is_no_parity(&self) -> bool {
247        **self == PARITYSEL_A::NO_PARITY
248    }
249    #[doc = "Checks if the value of the field is `EVEN_PARITY`"]
250    #[inline(always)]
251    pub fn is_even_parity(&self) -> bool {
252        **self == PARITYSEL_A::EVEN_PARITY
253    }
254    #[doc = "Checks if the value of the field is `ODD_PARITY`"]
255    #[inline(always)]
256    pub fn is_odd_parity(&self) -> bool {
257        **self == PARITYSEL_A::ODD_PARITY
258    }
259}
260impl core::ops::Deref for PARITYSEL_R {
261    type Target = crate::FieldReader<u8, PARITYSEL_A>;
262    #[inline(always)]
263    fn deref(&self) -> &Self::Target {
264        &self.0
265    }
266}
267#[doc = "Field `PARITYSEL` writer - Selects what type of parity is used by the USART."]
268pub struct PARITYSEL_W<'a> {
269    w: &'a mut W,
270}
271impl<'a> PARITYSEL_W<'a> {
272    #[doc = r"Writes `variant` to the field"]
273    #[inline(always)]
274    pub fn variant(self, variant: PARITYSEL_A) -> &'a mut W {
275        unsafe { self.bits(variant.into()) }
276    }
277    #[doc = "No parity."]
278    #[inline(always)]
279    pub fn no_parity(self) -> &'a mut W {
280        self.variant(PARITYSEL_A::NO_PARITY)
281    }
282    #[doc = "Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
283    #[inline(always)]
284    pub fn even_parity(self) -> &'a mut W {
285        self.variant(PARITYSEL_A::EVEN_PARITY)
286    }
287    #[doc = "Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
288    #[inline(always)]
289    pub fn odd_parity(self) -> &'a mut W {
290        self.variant(PARITYSEL_A::ODD_PARITY)
291    }
292    #[doc = r"Writes raw bits to the field"]
293    #[inline(always)]
294    pub unsafe fn bits(self, value: u8) -> &'a mut W {
295        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
296        self.w
297    }
298}
299#[doc = "Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.\n\nValue on reset: 0"]
300#[derive(Clone, Copy, Debug, PartialEq)]
301pub enum STOPLEN_A {
302    #[doc = "0: 1 stop bit."]
303    BIT_1 = 0,
304    #[doc = "1: 2 stop bits. This setting should only be used for asynchronous communication."]
305    BITS_2 = 1,
306}
307impl From<STOPLEN_A> for bool {
308    #[inline(always)]
309    fn from(variant: STOPLEN_A) -> Self {
310        variant as u8 != 0
311    }
312}
313#[doc = "Field `STOPLEN` reader - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
314pub struct STOPLEN_R(crate::FieldReader<bool, STOPLEN_A>);
315impl STOPLEN_R {
316    #[inline(always)]
317    pub(crate) fn new(bits: bool) -> Self {
318        STOPLEN_R(crate::FieldReader::new(bits))
319    }
320    #[doc = r"Get enumerated values variant"]
321    #[inline(always)]
322    pub fn variant(&self) -> STOPLEN_A {
323        match self.bits {
324            false => STOPLEN_A::BIT_1,
325            true => STOPLEN_A::BITS_2,
326        }
327    }
328    #[doc = "Checks if the value of the field is `BIT_1`"]
329    #[inline(always)]
330    pub fn is_bit_1(&self) -> bool {
331        **self == STOPLEN_A::BIT_1
332    }
333    #[doc = "Checks if the value of the field is `BITS_2`"]
334    #[inline(always)]
335    pub fn is_bits_2(&self) -> bool {
336        **self == STOPLEN_A::BITS_2
337    }
338}
339impl core::ops::Deref for STOPLEN_R {
340    type Target = crate::FieldReader<bool, STOPLEN_A>;
341    #[inline(always)]
342    fn deref(&self) -> &Self::Target {
343        &self.0
344    }
345}
346#[doc = "Field `STOPLEN` writer - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
347pub struct STOPLEN_W<'a> {
348    w: &'a mut W,
349}
350impl<'a> STOPLEN_W<'a> {
351    #[doc = r"Writes `variant` to the field"]
352    #[inline(always)]
353    pub fn variant(self, variant: STOPLEN_A) -> &'a mut W {
354        self.bit(variant.into())
355    }
356    #[doc = "1 stop bit."]
357    #[inline(always)]
358    pub fn bit_1(self) -> &'a mut W {
359        self.variant(STOPLEN_A::BIT_1)
360    }
361    #[doc = "2 stop bits. This setting should only be used for asynchronous communication."]
362    #[inline(always)]
363    pub fn bits_2(self) -> &'a mut W {
364        self.variant(STOPLEN_A::BITS_2)
365    }
366    #[doc = r"Sets the field bit"]
367    #[inline(always)]
368    pub fn set_bit(self) -> &'a mut W {
369        self.bit(true)
370    }
371    #[doc = r"Clears the field bit"]
372    #[inline(always)]
373    pub fn clear_bit(self) -> &'a mut W {
374        self.bit(false)
375    }
376    #[doc = r"Writes raw bits to the field"]
377    #[inline(always)]
378    pub fn bit(self, value: bool) -> &'a mut W {
379        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
380        self.w
381    }
382}
383#[doc = "Selects standard or 32 kHz clocking mode.\n\nValue on reset: 0"]
384#[derive(Clone, Copy, Debug, PartialEq)]
385pub enum MODE32K_A {
386    #[doc = "0: Disabled. USART uses standard clocking."]
387    DISABLED = 0,
388    #[doc = "1: Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme."]
389    ENABLED = 1,
390}
391impl From<MODE32K_A> for bool {
392    #[inline(always)]
393    fn from(variant: MODE32K_A) -> Self {
394        variant as u8 != 0
395    }
396}
397#[doc = "Field `MODE32K` reader - Selects standard or 32 kHz clocking mode."]
398pub struct MODE32K_R(crate::FieldReader<bool, MODE32K_A>);
399impl MODE32K_R {
400    #[inline(always)]
401    pub(crate) fn new(bits: bool) -> Self {
402        MODE32K_R(crate::FieldReader::new(bits))
403    }
404    #[doc = r"Get enumerated values variant"]
405    #[inline(always)]
406    pub fn variant(&self) -> MODE32K_A {
407        match self.bits {
408            false => MODE32K_A::DISABLED,
409            true => MODE32K_A::ENABLED,
410        }
411    }
412    #[doc = "Checks if the value of the field is `DISABLED`"]
413    #[inline(always)]
414    pub fn is_disabled(&self) -> bool {
415        **self == MODE32K_A::DISABLED
416    }
417    #[doc = "Checks if the value of the field is `ENABLED`"]
418    #[inline(always)]
419    pub fn is_enabled(&self) -> bool {
420        **self == MODE32K_A::ENABLED
421    }
422}
423impl core::ops::Deref for MODE32K_R {
424    type Target = crate::FieldReader<bool, MODE32K_A>;
425    #[inline(always)]
426    fn deref(&self) -> &Self::Target {
427        &self.0
428    }
429}
430#[doc = "Field `MODE32K` writer - Selects standard or 32 kHz clocking mode."]
431pub struct MODE32K_W<'a> {
432    w: &'a mut W,
433}
434impl<'a> MODE32K_W<'a> {
435    #[doc = r"Writes `variant` to the field"]
436    #[inline(always)]
437    pub fn variant(self, variant: MODE32K_A) -> &'a mut W {
438        self.bit(variant.into())
439    }
440    #[doc = "Disabled. USART uses standard clocking."]
441    #[inline(always)]
442    pub fn disabled(self) -> &'a mut W {
443        self.variant(MODE32K_A::DISABLED)
444    }
445    #[doc = "Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme."]
446    #[inline(always)]
447    pub fn enabled(self) -> &'a mut W {
448        self.variant(MODE32K_A::ENABLED)
449    }
450    #[doc = r"Sets the field bit"]
451    #[inline(always)]
452    pub fn set_bit(self) -> &'a mut W {
453        self.bit(true)
454    }
455    #[doc = r"Clears the field bit"]
456    #[inline(always)]
457    pub fn clear_bit(self) -> &'a mut W {
458        self.bit(false)
459    }
460    #[doc = r"Writes raw bits to the field"]
461    #[inline(always)]
462    pub fn bit(self, value: bool) -> &'a mut W {
463        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
464        self.w
465    }
466}
467#[doc = "LIN break mode enable.\n\nValue on reset: 0"]
468#[derive(Clone, Copy, Debug, PartialEq)]
469pub enum LINMODE_A {
470    #[doc = "0: Disabled. Break detect and generate is configured for normal operation."]
471    DISABLED = 0,
472    #[doc = "1: Enabled. Break detect and generate is configured for LIN bus operation."]
473    ENABLED = 1,
474}
475impl From<LINMODE_A> for bool {
476    #[inline(always)]
477    fn from(variant: LINMODE_A) -> Self {
478        variant as u8 != 0
479    }
480}
481#[doc = "Field `LINMODE` reader - LIN break mode enable."]
482pub struct LINMODE_R(crate::FieldReader<bool, LINMODE_A>);
483impl LINMODE_R {
484    #[inline(always)]
485    pub(crate) fn new(bits: bool) -> Self {
486        LINMODE_R(crate::FieldReader::new(bits))
487    }
488    #[doc = r"Get enumerated values variant"]
489    #[inline(always)]
490    pub fn variant(&self) -> LINMODE_A {
491        match self.bits {
492            false => LINMODE_A::DISABLED,
493            true => LINMODE_A::ENABLED,
494        }
495    }
496    #[doc = "Checks if the value of the field is `DISABLED`"]
497    #[inline(always)]
498    pub fn is_disabled(&self) -> bool {
499        **self == LINMODE_A::DISABLED
500    }
501    #[doc = "Checks if the value of the field is `ENABLED`"]
502    #[inline(always)]
503    pub fn is_enabled(&self) -> bool {
504        **self == LINMODE_A::ENABLED
505    }
506}
507impl core::ops::Deref for LINMODE_R {
508    type Target = crate::FieldReader<bool, LINMODE_A>;
509    #[inline(always)]
510    fn deref(&self) -> &Self::Target {
511        &self.0
512    }
513}
514#[doc = "Field `LINMODE` writer - LIN break mode enable."]
515pub struct LINMODE_W<'a> {
516    w: &'a mut W,
517}
518impl<'a> LINMODE_W<'a> {
519    #[doc = r"Writes `variant` to the field"]
520    #[inline(always)]
521    pub fn variant(self, variant: LINMODE_A) -> &'a mut W {
522        self.bit(variant.into())
523    }
524    #[doc = "Disabled. Break detect and generate is configured for normal operation."]
525    #[inline(always)]
526    pub fn disabled(self) -> &'a mut W {
527        self.variant(LINMODE_A::DISABLED)
528    }
529    #[doc = "Enabled. Break detect and generate is configured for LIN bus operation."]
530    #[inline(always)]
531    pub fn enabled(self) -> &'a mut W {
532        self.variant(LINMODE_A::ENABLED)
533    }
534    #[doc = r"Sets the field bit"]
535    #[inline(always)]
536    pub fn set_bit(self) -> &'a mut W {
537        self.bit(true)
538    }
539    #[doc = r"Clears the field bit"]
540    #[inline(always)]
541    pub fn clear_bit(self) -> &'a mut W {
542        self.bit(false)
543    }
544    #[doc = r"Writes raw bits to the field"]
545    #[inline(always)]
546    pub fn bit(self, value: bool) -> &'a mut W {
547        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
548        self.w
549    }
550}
551#[doc = "CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.\n\nValue on reset: 0"]
552#[derive(Clone, Copy, Debug, PartialEq)]
553pub enum CTSEN_A {
554    #[doc = "0: No flow control. The transmitter does not receive any automatic flow control signal."]
555    DISABLED = 0,
556    #[doc = "1: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
557    ENABLED = 1,
558}
559impl From<CTSEN_A> for bool {
560    #[inline(always)]
561    fn from(variant: CTSEN_A) -> Self {
562        variant as u8 != 0
563    }
564}
565#[doc = "Field `CTSEN` reader - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
566pub struct CTSEN_R(crate::FieldReader<bool, CTSEN_A>);
567impl CTSEN_R {
568    #[inline(always)]
569    pub(crate) fn new(bits: bool) -> Self {
570        CTSEN_R(crate::FieldReader::new(bits))
571    }
572    #[doc = r"Get enumerated values variant"]
573    #[inline(always)]
574    pub fn variant(&self) -> CTSEN_A {
575        match self.bits {
576            false => CTSEN_A::DISABLED,
577            true => CTSEN_A::ENABLED,
578        }
579    }
580    #[doc = "Checks if the value of the field is `DISABLED`"]
581    #[inline(always)]
582    pub fn is_disabled(&self) -> bool {
583        **self == CTSEN_A::DISABLED
584    }
585    #[doc = "Checks if the value of the field is `ENABLED`"]
586    #[inline(always)]
587    pub fn is_enabled(&self) -> bool {
588        **self == CTSEN_A::ENABLED
589    }
590}
591impl core::ops::Deref for CTSEN_R {
592    type Target = crate::FieldReader<bool, CTSEN_A>;
593    #[inline(always)]
594    fn deref(&self) -> &Self::Target {
595        &self.0
596    }
597}
598#[doc = "Field `CTSEN` writer - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
599pub struct CTSEN_W<'a> {
600    w: &'a mut W,
601}
602impl<'a> CTSEN_W<'a> {
603    #[doc = r"Writes `variant` to the field"]
604    #[inline(always)]
605    pub fn variant(self, variant: CTSEN_A) -> &'a mut W {
606        self.bit(variant.into())
607    }
608    #[doc = "No flow control. The transmitter does not receive any automatic flow control signal."]
609    #[inline(always)]
610    pub fn disabled(self) -> &'a mut W {
611        self.variant(CTSEN_A::DISABLED)
612    }
613    #[doc = "Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
614    #[inline(always)]
615    pub fn enabled(self) -> &'a mut W {
616        self.variant(CTSEN_A::ENABLED)
617    }
618    #[doc = r"Sets the field bit"]
619    #[inline(always)]
620    pub fn set_bit(self) -> &'a mut W {
621        self.bit(true)
622    }
623    #[doc = r"Clears the field bit"]
624    #[inline(always)]
625    pub fn clear_bit(self) -> &'a mut W {
626        self.bit(false)
627    }
628    #[doc = r"Writes raw bits to the field"]
629    #[inline(always)]
630    pub fn bit(self, value: bool) -> &'a mut W {
631        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
632        self.w
633    }
634}
635#[doc = "Selects synchronous or asynchronous operation.\n\nValue on reset: 0"]
636#[derive(Clone, Copy, Debug, PartialEq)]
637pub enum SYNCEN_A {
638    #[doc = "0: Asynchronous mode."]
639    ASYNCHRONOUS_MODE = 0,
640    #[doc = "1: Synchronous mode."]
641    SYNCHRONOUS_MODE = 1,
642}
643impl From<SYNCEN_A> for bool {
644    #[inline(always)]
645    fn from(variant: SYNCEN_A) -> Self {
646        variant as u8 != 0
647    }
648}
649#[doc = "Field `SYNCEN` reader - Selects synchronous or asynchronous operation."]
650pub struct SYNCEN_R(crate::FieldReader<bool, SYNCEN_A>);
651impl SYNCEN_R {
652    #[inline(always)]
653    pub(crate) fn new(bits: bool) -> Self {
654        SYNCEN_R(crate::FieldReader::new(bits))
655    }
656    #[doc = r"Get enumerated values variant"]
657    #[inline(always)]
658    pub fn variant(&self) -> SYNCEN_A {
659        match self.bits {
660            false => SYNCEN_A::ASYNCHRONOUS_MODE,
661            true => SYNCEN_A::SYNCHRONOUS_MODE,
662        }
663    }
664    #[doc = "Checks if the value of the field is `ASYNCHRONOUS_MODE`"]
665    #[inline(always)]
666    pub fn is_asynchronous_mode(&self) -> bool {
667        **self == SYNCEN_A::ASYNCHRONOUS_MODE
668    }
669    #[doc = "Checks if the value of the field is `SYNCHRONOUS_MODE`"]
670    #[inline(always)]
671    pub fn is_synchronous_mode(&self) -> bool {
672        **self == SYNCEN_A::SYNCHRONOUS_MODE
673    }
674}
675impl core::ops::Deref for SYNCEN_R {
676    type Target = crate::FieldReader<bool, SYNCEN_A>;
677    #[inline(always)]
678    fn deref(&self) -> &Self::Target {
679        &self.0
680    }
681}
682#[doc = "Field `SYNCEN` writer - Selects synchronous or asynchronous operation."]
683pub struct SYNCEN_W<'a> {
684    w: &'a mut W,
685}
686impl<'a> SYNCEN_W<'a> {
687    #[doc = r"Writes `variant` to the field"]
688    #[inline(always)]
689    pub fn variant(self, variant: SYNCEN_A) -> &'a mut W {
690        self.bit(variant.into())
691    }
692    #[doc = "Asynchronous mode."]
693    #[inline(always)]
694    pub fn asynchronous_mode(self) -> &'a mut W {
695        self.variant(SYNCEN_A::ASYNCHRONOUS_MODE)
696    }
697    #[doc = "Synchronous mode."]
698    #[inline(always)]
699    pub fn synchronous_mode(self) -> &'a mut W {
700        self.variant(SYNCEN_A::SYNCHRONOUS_MODE)
701    }
702    #[doc = r"Sets the field bit"]
703    #[inline(always)]
704    pub fn set_bit(self) -> &'a mut W {
705        self.bit(true)
706    }
707    #[doc = r"Clears the field bit"]
708    #[inline(always)]
709    pub fn clear_bit(self) -> &'a mut W {
710        self.bit(false)
711    }
712    #[doc = r"Writes raw bits to the field"]
713    #[inline(always)]
714    pub fn bit(self, value: bool) -> &'a mut W {
715        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
716        self.w
717    }
718}
719#[doc = "Selects the clock polarity and sampling edge of received data in synchronous mode.\n\nValue on reset: 0"]
720#[derive(Clone, Copy, Debug, PartialEq)]
721pub enum CLKPOL_A {
722    #[doc = "0: Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
723    FALLING_EDGE = 0,
724    #[doc = "1: Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
725    RISING_EDGE = 1,
726}
727impl From<CLKPOL_A> for bool {
728    #[inline(always)]
729    fn from(variant: CLKPOL_A) -> Self {
730        variant as u8 != 0
731    }
732}
733#[doc = "Field `CLKPOL` reader - Selects the clock polarity and sampling edge of received data in synchronous mode."]
734pub struct CLKPOL_R(crate::FieldReader<bool, CLKPOL_A>);
735impl CLKPOL_R {
736    #[inline(always)]
737    pub(crate) fn new(bits: bool) -> Self {
738        CLKPOL_R(crate::FieldReader::new(bits))
739    }
740    #[doc = r"Get enumerated values variant"]
741    #[inline(always)]
742    pub fn variant(&self) -> CLKPOL_A {
743        match self.bits {
744            false => CLKPOL_A::FALLING_EDGE,
745            true => CLKPOL_A::RISING_EDGE,
746        }
747    }
748    #[doc = "Checks if the value of the field is `FALLING_EDGE`"]
749    #[inline(always)]
750    pub fn is_falling_edge(&self) -> bool {
751        **self == CLKPOL_A::FALLING_EDGE
752    }
753    #[doc = "Checks if the value of the field is `RISING_EDGE`"]
754    #[inline(always)]
755    pub fn is_rising_edge(&self) -> bool {
756        **self == CLKPOL_A::RISING_EDGE
757    }
758}
759impl core::ops::Deref for CLKPOL_R {
760    type Target = crate::FieldReader<bool, CLKPOL_A>;
761    #[inline(always)]
762    fn deref(&self) -> &Self::Target {
763        &self.0
764    }
765}
766#[doc = "Field `CLKPOL` writer - Selects the clock polarity and sampling edge of received data in synchronous mode."]
767pub struct CLKPOL_W<'a> {
768    w: &'a mut W,
769}
770impl<'a> CLKPOL_W<'a> {
771    #[doc = r"Writes `variant` to the field"]
772    #[inline(always)]
773    pub fn variant(self, variant: CLKPOL_A) -> &'a mut W {
774        self.bit(variant.into())
775    }
776    #[doc = "Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
777    #[inline(always)]
778    pub fn falling_edge(self) -> &'a mut W {
779        self.variant(CLKPOL_A::FALLING_EDGE)
780    }
781    #[doc = "Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
782    #[inline(always)]
783    pub fn rising_edge(self) -> &'a mut W {
784        self.variant(CLKPOL_A::RISING_EDGE)
785    }
786    #[doc = r"Sets the field bit"]
787    #[inline(always)]
788    pub fn set_bit(self) -> &'a mut W {
789        self.bit(true)
790    }
791    #[doc = r"Clears the field bit"]
792    #[inline(always)]
793    pub fn clear_bit(self) -> &'a mut W {
794        self.bit(false)
795    }
796    #[doc = r"Writes raw bits to the field"]
797    #[inline(always)]
798    pub fn bit(self, value: bool) -> &'a mut W {
799        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
800        self.w
801    }
802}
803#[doc = "Synchronous mode Master select.\n\nValue on reset: 0"]
804#[derive(Clone, Copy, Debug, PartialEq)]
805pub enum SYNCMST_A {
806    #[doc = "0: Slave. When synchronous mode is enabled, the USART is a slave."]
807    SLAVE = 0,
808    #[doc = "1: Master. When synchronous mode is enabled, the USART is a master."]
809    MASTER = 1,
810}
811impl From<SYNCMST_A> for bool {
812    #[inline(always)]
813    fn from(variant: SYNCMST_A) -> Self {
814        variant as u8 != 0
815    }
816}
817#[doc = "Field `SYNCMST` reader - Synchronous mode Master select."]
818pub struct SYNCMST_R(crate::FieldReader<bool, SYNCMST_A>);
819impl SYNCMST_R {
820    #[inline(always)]
821    pub(crate) fn new(bits: bool) -> Self {
822        SYNCMST_R(crate::FieldReader::new(bits))
823    }
824    #[doc = r"Get enumerated values variant"]
825    #[inline(always)]
826    pub fn variant(&self) -> SYNCMST_A {
827        match self.bits {
828            false => SYNCMST_A::SLAVE,
829            true => SYNCMST_A::MASTER,
830        }
831    }
832    #[doc = "Checks if the value of the field is `SLAVE`"]
833    #[inline(always)]
834    pub fn is_slave(&self) -> bool {
835        **self == SYNCMST_A::SLAVE
836    }
837    #[doc = "Checks if the value of the field is `MASTER`"]
838    #[inline(always)]
839    pub fn is_master(&self) -> bool {
840        **self == SYNCMST_A::MASTER
841    }
842}
843impl core::ops::Deref for SYNCMST_R {
844    type Target = crate::FieldReader<bool, SYNCMST_A>;
845    #[inline(always)]
846    fn deref(&self) -> &Self::Target {
847        &self.0
848    }
849}
850#[doc = "Field `SYNCMST` writer - Synchronous mode Master select."]
851pub struct SYNCMST_W<'a> {
852    w: &'a mut W,
853}
854impl<'a> SYNCMST_W<'a> {
855    #[doc = r"Writes `variant` to the field"]
856    #[inline(always)]
857    pub fn variant(self, variant: SYNCMST_A) -> &'a mut W {
858        self.bit(variant.into())
859    }
860    #[doc = "Slave. When synchronous mode is enabled, the USART is a slave."]
861    #[inline(always)]
862    pub fn slave(self) -> &'a mut W {
863        self.variant(SYNCMST_A::SLAVE)
864    }
865    #[doc = "Master. When synchronous mode is enabled, the USART is a master."]
866    #[inline(always)]
867    pub fn master(self) -> &'a mut W {
868        self.variant(SYNCMST_A::MASTER)
869    }
870    #[doc = r"Sets the field bit"]
871    #[inline(always)]
872    pub fn set_bit(self) -> &'a mut W {
873        self.bit(true)
874    }
875    #[doc = r"Clears the field bit"]
876    #[inline(always)]
877    pub fn clear_bit(self) -> &'a mut W {
878        self.bit(false)
879    }
880    #[doc = r"Writes raw bits to the field"]
881    #[inline(always)]
882    pub fn bit(self, value: bool) -> &'a mut W {
883        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
884        self.w
885    }
886}
887#[doc = "Selects data loopback mode.\n\nValue on reset: 0"]
888#[derive(Clone, Copy, Debug, PartialEq)]
889pub enum LOOP_A {
890    #[doc = "0: Normal operation."]
891    NORMAL = 0,
892    #[doc = "1: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
893    LOOPBACK = 1,
894}
895impl From<LOOP_A> for bool {
896    #[inline(always)]
897    fn from(variant: LOOP_A) -> Self {
898        variant as u8 != 0
899    }
900}
901#[doc = "Field `LOOP` reader - Selects data loopback mode."]
902pub struct LOOP_R(crate::FieldReader<bool, LOOP_A>);
903impl LOOP_R {
904    #[inline(always)]
905    pub(crate) fn new(bits: bool) -> Self {
906        LOOP_R(crate::FieldReader::new(bits))
907    }
908    #[doc = r"Get enumerated values variant"]
909    #[inline(always)]
910    pub fn variant(&self) -> LOOP_A {
911        match self.bits {
912            false => LOOP_A::NORMAL,
913            true => LOOP_A::LOOPBACK,
914        }
915    }
916    #[doc = "Checks if the value of the field is `NORMAL`"]
917    #[inline(always)]
918    pub fn is_normal(&self) -> bool {
919        **self == LOOP_A::NORMAL
920    }
921    #[doc = "Checks if the value of the field is `LOOPBACK`"]
922    #[inline(always)]
923    pub fn is_loopback(&self) -> bool {
924        **self == LOOP_A::LOOPBACK
925    }
926}
927impl core::ops::Deref for LOOP_R {
928    type Target = crate::FieldReader<bool, LOOP_A>;
929    #[inline(always)]
930    fn deref(&self) -> &Self::Target {
931        &self.0
932    }
933}
934#[doc = "Field `LOOP` writer - Selects data loopback mode."]
935pub struct LOOP_W<'a> {
936    w: &'a mut W,
937}
938impl<'a> LOOP_W<'a> {
939    #[doc = r"Writes `variant` to the field"]
940    #[inline(always)]
941    pub fn variant(self, variant: LOOP_A) -> &'a mut W {
942        self.bit(variant.into())
943    }
944    #[doc = "Normal operation."]
945    #[inline(always)]
946    pub fn normal(self) -> &'a mut W {
947        self.variant(LOOP_A::NORMAL)
948    }
949    #[doc = "Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
950    #[inline(always)]
951    pub fn loopback(self) -> &'a mut W {
952        self.variant(LOOP_A::LOOPBACK)
953    }
954    #[doc = r"Sets the field bit"]
955    #[inline(always)]
956    pub fn set_bit(self) -> &'a mut W {
957        self.bit(true)
958    }
959    #[doc = r"Clears the field bit"]
960    #[inline(always)]
961    pub fn clear_bit(self) -> &'a mut W {
962        self.bit(false)
963    }
964    #[doc = r"Writes raw bits to the field"]
965    #[inline(always)]
966    pub fn bit(self, value: bool) -> &'a mut W {
967        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
968        self.w
969    }
970}
971#[doc = "Output Enable Turnaround time enable for RS-485 operation.\n\nValue on reset: 0"]
972#[derive(Clone, Copy, Debug, PartialEq)]
973pub enum OETA_A {
974    #[doc = "0: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
975    DISABLED = 0,
976    #[doc = "1: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
977    ENABLED = 1,
978}
979impl From<OETA_A> for bool {
980    #[inline(always)]
981    fn from(variant: OETA_A) -> Self {
982        variant as u8 != 0
983    }
984}
985#[doc = "Field `OETA` reader - Output Enable Turnaround time enable for RS-485 operation."]
986pub struct OETA_R(crate::FieldReader<bool, OETA_A>);
987impl OETA_R {
988    #[inline(always)]
989    pub(crate) fn new(bits: bool) -> Self {
990        OETA_R(crate::FieldReader::new(bits))
991    }
992    #[doc = r"Get enumerated values variant"]
993    #[inline(always)]
994    pub fn variant(&self) -> OETA_A {
995        match self.bits {
996            false => OETA_A::DISABLED,
997            true => OETA_A::ENABLED,
998        }
999    }
1000    #[doc = "Checks if the value of the field is `DISABLED`"]
1001    #[inline(always)]
1002    pub fn is_disabled(&self) -> bool {
1003        **self == OETA_A::DISABLED
1004    }
1005    #[doc = "Checks if the value of the field is `ENABLED`"]
1006    #[inline(always)]
1007    pub fn is_enabled(&self) -> bool {
1008        **self == OETA_A::ENABLED
1009    }
1010}
1011impl core::ops::Deref for OETA_R {
1012    type Target = crate::FieldReader<bool, OETA_A>;
1013    #[inline(always)]
1014    fn deref(&self) -> &Self::Target {
1015        &self.0
1016    }
1017}
1018#[doc = "Field `OETA` writer - Output Enable Turnaround time enable for RS-485 operation."]
1019pub struct OETA_W<'a> {
1020    w: &'a mut W,
1021}
1022impl<'a> OETA_W<'a> {
1023    #[doc = r"Writes `variant` to the field"]
1024    #[inline(always)]
1025    pub fn variant(self, variant: OETA_A) -> &'a mut W {
1026        self.bit(variant.into())
1027    }
1028    #[doc = "Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
1029    #[inline(always)]
1030    pub fn disabled(self) -> &'a mut W {
1031        self.variant(OETA_A::DISABLED)
1032    }
1033    #[doc = "Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
1034    #[inline(always)]
1035    pub fn enabled(self) -> &'a mut W {
1036        self.variant(OETA_A::ENABLED)
1037    }
1038    #[doc = r"Sets the field bit"]
1039    #[inline(always)]
1040    pub fn set_bit(self) -> &'a mut W {
1041        self.bit(true)
1042    }
1043    #[doc = r"Clears the field bit"]
1044    #[inline(always)]
1045    pub fn clear_bit(self) -> &'a mut W {
1046        self.bit(false)
1047    }
1048    #[doc = r"Writes raw bits to the field"]
1049    #[inline(always)]
1050    pub fn bit(self, value: bool) -> &'a mut W {
1051        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
1052        self.w
1053    }
1054}
1055#[doc = "Automatic Address matching enable.\n\nValue on reset: 0"]
1056#[derive(Clone, Copy, Debug, PartialEq)]
1057pub enum AUTOADDR_A {
1058    #[doc = "0: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
1059    DISABLED = 0,
1060    #[doc = "1: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
1061    ENABLED = 1,
1062}
1063impl From<AUTOADDR_A> for bool {
1064    #[inline(always)]
1065    fn from(variant: AUTOADDR_A) -> Self {
1066        variant as u8 != 0
1067    }
1068}
1069#[doc = "Field `AUTOADDR` reader - Automatic Address matching enable."]
1070pub struct AUTOADDR_R(crate::FieldReader<bool, AUTOADDR_A>);
1071impl AUTOADDR_R {
1072    #[inline(always)]
1073    pub(crate) fn new(bits: bool) -> Self {
1074        AUTOADDR_R(crate::FieldReader::new(bits))
1075    }
1076    #[doc = r"Get enumerated values variant"]
1077    #[inline(always)]
1078    pub fn variant(&self) -> AUTOADDR_A {
1079        match self.bits {
1080            false => AUTOADDR_A::DISABLED,
1081            true => AUTOADDR_A::ENABLED,
1082        }
1083    }
1084    #[doc = "Checks if the value of the field is `DISABLED`"]
1085    #[inline(always)]
1086    pub fn is_disabled(&self) -> bool {
1087        **self == AUTOADDR_A::DISABLED
1088    }
1089    #[doc = "Checks if the value of the field is `ENABLED`"]
1090    #[inline(always)]
1091    pub fn is_enabled(&self) -> bool {
1092        **self == AUTOADDR_A::ENABLED
1093    }
1094}
1095impl core::ops::Deref for AUTOADDR_R {
1096    type Target = crate::FieldReader<bool, AUTOADDR_A>;
1097    #[inline(always)]
1098    fn deref(&self) -> &Self::Target {
1099        &self.0
1100    }
1101}
1102#[doc = "Field `AUTOADDR` writer - Automatic Address matching enable."]
1103pub struct AUTOADDR_W<'a> {
1104    w: &'a mut W,
1105}
1106impl<'a> AUTOADDR_W<'a> {
1107    #[doc = r"Writes `variant` to the field"]
1108    #[inline(always)]
1109    pub fn variant(self, variant: AUTOADDR_A) -> &'a mut W {
1110        self.bit(variant.into())
1111    }
1112    #[doc = "Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
1113    #[inline(always)]
1114    pub fn disabled(self) -> &'a mut W {
1115        self.variant(AUTOADDR_A::DISABLED)
1116    }
1117    #[doc = "Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
1118    #[inline(always)]
1119    pub fn enabled(self) -> &'a mut W {
1120        self.variant(AUTOADDR_A::ENABLED)
1121    }
1122    #[doc = r"Sets the field bit"]
1123    #[inline(always)]
1124    pub fn set_bit(self) -> &'a mut W {
1125        self.bit(true)
1126    }
1127    #[doc = r"Clears the field bit"]
1128    #[inline(always)]
1129    pub fn clear_bit(self) -> &'a mut W {
1130        self.bit(false)
1131    }
1132    #[doc = r"Writes raw bits to the field"]
1133    #[inline(always)]
1134    pub fn bit(self, value: bool) -> &'a mut W {
1135        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
1136        self.w
1137    }
1138}
1139#[doc = "Output Enable Select.\n\nValue on reset: 0"]
1140#[derive(Clone, Copy, Debug, PartialEq)]
1141pub enum OESEL_A {
1142    #[doc = "0: Standard. The RTS signal is used as the standard flow control function."]
1143    STANDARD = 0,
1144    #[doc = "1: RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
1145    RS_485 = 1,
1146}
1147impl From<OESEL_A> for bool {
1148    #[inline(always)]
1149    fn from(variant: OESEL_A) -> Self {
1150        variant as u8 != 0
1151    }
1152}
1153#[doc = "Field `OESEL` reader - Output Enable Select."]
1154pub struct OESEL_R(crate::FieldReader<bool, OESEL_A>);
1155impl OESEL_R {
1156    #[inline(always)]
1157    pub(crate) fn new(bits: bool) -> Self {
1158        OESEL_R(crate::FieldReader::new(bits))
1159    }
1160    #[doc = r"Get enumerated values variant"]
1161    #[inline(always)]
1162    pub fn variant(&self) -> OESEL_A {
1163        match self.bits {
1164            false => OESEL_A::STANDARD,
1165            true => OESEL_A::RS_485,
1166        }
1167    }
1168    #[doc = "Checks if the value of the field is `STANDARD`"]
1169    #[inline(always)]
1170    pub fn is_standard(&self) -> bool {
1171        **self == OESEL_A::STANDARD
1172    }
1173    #[doc = "Checks if the value of the field is `RS_485`"]
1174    #[inline(always)]
1175    pub fn is_rs_485(&self) -> bool {
1176        **self == OESEL_A::RS_485
1177    }
1178}
1179impl core::ops::Deref for OESEL_R {
1180    type Target = crate::FieldReader<bool, OESEL_A>;
1181    #[inline(always)]
1182    fn deref(&self) -> &Self::Target {
1183        &self.0
1184    }
1185}
1186#[doc = "Field `OESEL` writer - Output Enable Select."]
1187pub struct OESEL_W<'a> {
1188    w: &'a mut W,
1189}
1190impl<'a> OESEL_W<'a> {
1191    #[doc = r"Writes `variant` to the field"]
1192    #[inline(always)]
1193    pub fn variant(self, variant: OESEL_A) -> &'a mut W {
1194        self.bit(variant.into())
1195    }
1196    #[doc = "Standard. The RTS signal is used as the standard flow control function."]
1197    #[inline(always)]
1198    pub fn standard(self) -> &'a mut W {
1199        self.variant(OESEL_A::STANDARD)
1200    }
1201    #[doc = "RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
1202    #[inline(always)]
1203    pub fn rs_485(self) -> &'a mut W {
1204        self.variant(OESEL_A::RS_485)
1205    }
1206    #[doc = r"Sets the field bit"]
1207    #[inline(always)]
1208    pub fn set_bit(self) -> &'a mut W {
1209        self.bit(true)
1210    }
1211    #[doc = r"Clears the field bit"]
1212    #[inline(always)]
1213    pub fn clear_bit(self) -> &'a mut W {
1214        self.bit(false)
1215    }
1216    #[doc = r"Writes raw bits to the field"]
1217    #[inline(always)]
1218    pub fn bit(self, value: bool) -> &'a mut W {
1219        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
1220        self.w
1221    }
1222}
1223#[doc = "Output Enable Polarity.\n\nValue on reset: 0"]
1224#[derive(Clone, Copy, Debug, PartialEq)]
1225pub enum OEPOL_A {
1226    #[doc = "0: Low. If selected by OESEL, the output enable is active low."]
1227    LOW = 0,
1228    #[doc = "1: High. If selected by OESEL, the output enable is active high."]
1229    HIGH = 1,
1230}
1231impl From<OEPOL_A> for bool {
1232    #[inline(always)]
1233    fn from(variant: OEPOL_A) -> Self {
1234        variant as u8 != 0
1235    }
1236}
1237#[doc = "Field `OEPOL` reader - Output Enable Polarity."]
1238pub struct OEPOL_R(crate::FieldReader<bool, OEPOL_A>);
1239impl OEPOL_R {
1240    #[inline(always)]
1241    pub(crate) fn new(bits: bool) -> Self {
1242        OEPOL_R(crate::FieldReader::new(bits))
1243    }
1244    #[doc = r"Get enumerated values variant"]
1245    #[inline(always)]
1246    pub fn variant(&self) -> OEPOL_A {
1247        match self.bits {
1248            false => OEPOL_A::LOW,
1249            true => OEPOL_A::HIGH,
1250        }
1251    }
1252    #[doc = "Checks if the value of the field is `LOW`"]
1253    #[inline(always)]
1254    pub fn is_low(&self) -> bool {
1255        **self == OEPOL_A::LOW
1256    }
1257    #[doc = "Checks if the value of the field is `HIGH`"]
1258    #[inline(always)]
1259    pub fn is_high(&self) -> bool {
1260        **self == OEPOL_A::HIGH
1261    }
1262}
1263impl core::ops::Deref for OEPOL_R {
1264    type Target = crate::FieldReader<bool, OEPOL_A>;
1265    #[inline(always)]
1266    fn deref(&self) -> &Self::Target {
1267        &self.0
1268    }
1269}
1270#[doc = "Field `OEPOL` writer - Output Enable Polarity."]
1271pub struct OEPOL_W<'a> {
1272    w: &'a mut W,
1273}
1274impl<'a> OEPOL_W<'a> {
1275    #[doc = r"Writes `variant` to the field"]
1276    #[inline(always)]
1277    pub fn variant(self, variant: OEPOL_A) -> &'a mut W {
1278        self.bit(variant.into())
1279    }
1280    #[doc = "Low. If selected by OESEL, the output enable is active low."]
1281    #[inline(always)]
1282    pub fn low(self) -> &'a mut W {
1283        self.variant(OEPOL_A::LOW)
1284    }
1285    #[doc = "High. If selected by OESEL, the output enable is active high."]
1286    #[inline(always)]
1287    pub fn high(self) -> &'a mut W {
1288        self.variant(OEPOL_A::HIGH)
1289    }
1290    #[doc = r"Sets the field bit"]
1291    #[inline(always)]
1292    pub fn set_bit(self) -> &'a mut W {
1293        self.bit(true)
1294    }
1295    #[doc = r"Clears the field bit"]
1296    #[inline(always)]
1297    pub fn clear_bit(self) -> &'a mut W {
1298        self.bit(false)
1299    }
1300    #[doc = r"Writes raw bits to the field"]
1301    #[inline(always)]
1302    pub fn bit(self, value: bool) -> &'a mut W {
1303        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
1304        self.w
1305    }
1306}
1307#[doc = "Receive data polarity.\n\nValue on reset: 0"]
1308#[derive(Clone, Copy, Debug, PartialEq)]
1309pub enum RXPOL_A {
1310    #[doc = "0: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1311    STANDARD = 0,
1312    #[doc = "1: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1313    INVERTED = 1,
1314}
1315impl From<RXPOL_A> for bool {
1316    #[inline(always)]
1317    fn from(variant: RXPOL_A) -> Self {
1318        variant as u8 != 0
1319    }
1320}
1321#[doc = "Field `RXPOL` reader - Receive data polarity."]
1322pub struct RXPOL_R(crate::FieldReader<bool, RXPOL_A>);
1323impl RXPOL_R {
1324    #[inline(always)]
1325    pub(crate) fn new(bits: bool) -> Self {
1326        RXPOL_R(crate::FieldReader::new(bits))
1327    }
1328    #[doc = r"Get enumerated values variant"]
1329    #[inline(always)]
1330    pub fn variant(&self) -> RXPOL_A {
1331        match self.bits {
1332            false => RXPOL_A::STANDARD,
1333            true => RXPOL_A::INVERTED,
1334        }
1335    }
1336    #[doc = "Checks if the value of the field is `STANDARD`"]
1337    #[inline(always)]
1338    pub fn is_standard(&self) -> bool {
1339        **self == RXPOL_A::STANDARD
1340    }
1341    #[doc = "Checks if the value of the field is `INVERTED`"]
1342    #[inline(always)]
1343    pub fn is_inverted(&self) -> bool {
1344        **self == RXPOL_A::INVERTED
1345    }
1346}
1347impl core::ops::Deref for RXPOL_R {
1348    type Target = crate::FieldReader<bool, RXPOL_A>;
1349    #[inline(always)]
1350    fn deref(&self) -> &Self::Target {
1351        &self.0
1352    }
1353}
1354#[doc = "Field `RXPOL` writer - Receive data polarity."]
1355pub struct RXPOL_W<'a> {
1356    w: &'a mut W,
1357}
1358impl<'a> RXPOL_W<'a> {
1359    #[doc = r"Writes `variant` to the field"]
1360    #[inline(always)]
1361    pub fn variant(self, variant: RXPOL_A) -> &'a mut W {
1362        self.bit(variant.into())
1363    }
1364    #[doc = "Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1365    #[inline(always)]
1366    pub fn standard(self) -> &'a mut W {
1367        self.variant(RXPOL_A::STANDARD)
1368    }
1369    #[doc = "Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1370    #[inline(always)]
1371    pub fn inverted(self) -> &'a mut W {
1372        self.variant(RXPOL_A::INVERTED)
1373    }
1374    #[doc = r"Sets the field bit"]
1375    #[inline(always)]
1376    pub fn set_bit(self) -> &'a mut W {
1377        self.bit(true)
1378    }
1379    #[doc = r"Clears the field bit"]
1380    #[inline(always)]
1381    pub fn clear_bit(self) -> &'a mut W {
1382        self.bit(false)
1383    }
1384    #[doc = r"Writes raw bits to the field"]
1385    #[inline(always)]
1386    pub fn bit(self, value: bool) -> &'a mut W {
1387        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
1388        self.w
1389    }
1390}
1391#[doc = "Transmit data polarity.\n\nValue on reset: 0"]
1392#[derive(Clone, Copy, Debug, PartialEq)]
1393pub enum TXPOL_A {
1394    #[doc = "0: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1395    STANDARD = 0,
1396    #[doc = "1: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1397    INVERTED = 1,
1398}
1399impl From<TXPOL_A> for bool {
1400    #[inline(always)]
1401    fn from(variant: TXPOL_A) -> Self {
1402        variant as u8 != 0
1403    }
1404}
1405#[doc = "Field `TXPOL` reader - Transmit data polarity."]
1406pub struct TXPOL_R(crate::FieldReader<bool, TXPOL_A>);
1407impl TXPOL_R {
1408    #[inline(always)]
1409    pub(crate) fn new(bits: bool) -> Self {
1410        TXPOL_R(crate::FieldReader::new(bits))
1411    }
1412    #[doc = r"Get enumerated values variant"]
1413    #[inline(always)]
1414    pub fn variant(&self) -> TXPOL_A {
1415        match self.bits {
1416            false => TXPOL_A::STANDARD,
1417            true => TXPOL_A::INVERTED,
1418        }
1419    }
1420    #[doc = "Checks if the value of the field is `STANDARD`"]
1421    #[inline(always)]
1422    pub fn is_standard(&self) -> bool {
1423        **self == TXPOL_A::STANDARD
1424    }
1425    #[doc = "Checks if the value of the field is `INVERTED`"]
1426    #[inline(always)]
1427    pub fn is_inverted(&self) -> bool {
1428        **self == TXPOL_A::INVERTED
1429    }
1430}
1431impl core::ops::Deref for TXPOL_R {
1432    type Target = crate::FieldReader<bool, TXPOL_A>;
1433    #[inline(always)]
1434    fn deref(&self) -> &Self::Target {
1435        &self.0
1436    }
1437}
1438#[doc = "Field `TXPOL` writer - Transmit data polarity."]
1439pub struct TXPOL_W<'a> {
1440    w: &'a mut W,
1441}
1442impl<'a> TXPOL_W<'a> {
1443    #[doc = r"Writes `variant` to the field"]
1444    #[inline(always)]
1445    pub fn variant(self, variant: TXPOL_A) -> &'a mut W {
1446        self.bit(variant.into())
1447    }
1448    #[doc = "Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1449    #[inline(always)]
1450    pub fn standard(self) -> &'a mut W {
1451        self.variant(TXPOL_A::STANDARD)
1452    }
1453    #[doc = "Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1454    #[inline(always)]
1455    pub fn inverted(self) -> &'a mut W {
1456        self.variant(TXPOL_A::INVERTED)
1457    }
1458    #[doc = r"Sets the field bit"]
1459    #[inline(always)]
1460    pub fn set_bit(self) -> &'a mut W {
1461        self.bit(true)
1462    }
1463    #[doc = r"Clears the field bit"]
1464    #[inline(always)]
1465    pub fn clear_bit(self) -> &'a mut W {
1466        self.bit(false)
1467    }
1468    #[doc = r"Writes raw bits to the field"]
1469    #[inline(always)]
1470    pub fn bit(self, value: bool) -> &'a mut W {
1471        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
1472        self.w
1473    }
1474}
1475impl R {
1476    #[doc = "Bit 0 - USART Enable."]
1477    #[inline(always)]
1478    pub fn enable(&self) -> ENABLE_R {
1479        ENABLE_R::new((self.bits & 0x01) != 0)
1480    }
1481    #[doc = "Bits 2:3 - Selects the data size for the USART."]
1482    #[inline(always)]
1483    pub fn datalen(&self) -> DATALEN_R {
1484        DATALEN_R::new(((self.bits >> 2) & 0x03) as u8)
1485    }
1486    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
1487    #[inline(always)]
1488    pub fn paritysel(&self) -> PARITYSEL_R {
1489        PARITYSEL_R::new(((self.bits >> 4) & 0x03) as u8)
1490    }
1491    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
1492    #[inline(always)]
1493    pub fn stoplen(&self) -> STOPLEN_R {
1494        STOPLEN_R::new(((self.bits >> 6) & 0x01) != 0)
1495    }
1496    #[doc = "Bit 7 - Selects standard or 32 kHz clocking mode."]
1497    #[inline(always)]
1498    pub fn mode32k(&self) -> MODE32K_R {
1499        MODE32K_R::new(((self.bits >> 7) & 0x01) != 0)
1500    }
1501    #[doc = "Bit 8 - LIN break mode enable."]
1502    #[inline(always)]
1503    pub fn linmode(&self) -> LINMODE_R {
1504        LINMODE_R::new(((self.bits >> 8) & 0x01) != 0)
1505    }
1506    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
1507    #[inline(always)]
1508    pub fn ctsen(&self) -> CTSEN_R {
1509        CTSEN_R::new(((self.bits >> 9) & 0x01) != 0)
1510    }
1511    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1512    #[inline(always)]
1513    pub fn syncen(&self) -> SYNCEN_R {
1514        SYNCEN_R::new(((self.bits >> 11) & 0x01) != 0)
1515    }
1516    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1517    #[inline(always)]
1518    pub fn clkpol(&self) -> CLKPOL_R {
1519        CLKPOL_R::new(((self.bits >> 12) & 0x01) != 0)
1520    }
1521    #[doc = "Bit 14 - Synchronous mode Master select."]
1522    #[inline(always)]
1523    pub fn syncmst(&self) -> SYNCMST_R {
1524        SYNCMST_R::new(((self.bits >> 14) & 0x01) != 0)
1525    }
1526    #[doc = "Bit 15 - Selects data loopback mode."]
1527    #[inline(always)]
1528    pub fn loop_(&self) -> LOOP_R {
1529        LOOP_R::new(((self.bits >> 15) & 0x01) != 0)
1530    }
1531    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1532    #[inline(always)]
1533    pub fn oeta(&self) -> OETA_R {
1534        OETA_R::new(((self.bits >> 18) & 0x01) != 0)
1535    }
1536    #[doc = "Bit 19 - Automatic Address matching enable."]
1537    #[inline(always)]
1538    pub fn autoaddr(&self) -> AUTOADDR_R {
1539        AUTOADDR_R::new(((self.bits >> 19) & 0x01) != 0)
1540    }
1541    #[doc = "Bit 20 - Output Enable Select."]
1542    #[inline(always)]
1543    pub fn oesel(&self) -> OESEL_R {
1544        OESEL_R::new(((self.bits >> 20) & 0x01) != 0)
1545    }
1546    #[doc = "Bit 21 - Output Enable Polarity."]
1547    #[inline(always)]
1548    pub fn oepol(&self) -> OEPOL_R {
1549        OEPOL_R::new(((self.bits >> 21) & 0x01) != 0)
1550    }
1551    #[doc = "Bit 22 - Receive data polarity."]
1552    #[inline(always)]
1553    pub fn rxpol(&self) -> RXPOL_R {
1554        RXPOL_R::new(((self.bits >> 22) & 0x01) != 0)
1555    }
1556    #[doc = "Bit 23 - Transmit data polarity."]
1557    #[inline(always)]
1558    pub fn txpol(&self) -> TXPOL_R {
1559        TXPOL_R::new(((self.bits >> 23) & 0x01) != 0)
1560    }
1561}
1562impl W {
1563    #[doc = "Bit 0 - USART Enable."]
1564    #[inline(always)]
1565    pub fn enable(&mut self) -> ENABLE_W {
1566        ENABLE_W { w: self }
1567    }
1568    #[doc = "Bits 2:3 - Selects the data size for the USART."]
1569    #[inline(always)]
1570    pub fn datalen(&mut self) -> DATALEN_W {
1571        DATALEN_W { w: self }
1572    }
1573    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
1574    #[inline(always)]
1575    pub fn paritysel(&mut self) -> PARITYSEL_W {
1576        PARITYSEL_W { w: self }
1577    }
1578    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
1579    #[inline(always)]
1580    pub fn stoplen(&mut self) -> STOPLEN_W {
1581        STOPLEN_W { w: self }
1582    }
1583    #[doc = "Bit 7 - Selects standard or 32 kHz clocking mode."]
1584    #[inline(always)]
1585    pub fn mode32k(&mut self) -> MODE32K_W {
1586        MODE32K_W { w: self }
1587    }
1588    #[doc = "Bit 8 - LIN break mode enable."]
1589    #[inline(always)]
1590    pub fn linmode(&mut self) -> LINMODE_W {
1591        LINMODE_W { w: self }
1592    }
1593    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
1594    #[inline(always)]
1595    pub fn ctsen(&mut self) -> CTSEN_W {
1596        CTSEN_W { w: self }
1597    }
1598    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1599    #[inline(always)]
1600    pub fn syncen(&mut self) -> SYNCEN_W {
1601        SYNCEN_W { w: self }
1602    }
1603    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1604    #[inline(always)]
1605    pub fn clkpol(&mut self) -> CLKPOL_W {
1606        CLKPOL_W { w: self }
1607    }
1608    #[doc = "Bit 14 - Synchronous mode Master select."]
1609    #[inline(always)]
1610    pub fn syncmst(&mut self) -> SYNCMST_W {
1611        SYNCMST_W { w: self }
1612    }
1613    #[doc = "Bit 15 - Selects data loopback mode."]
1614    #[inline(always)]
1615    pub fn loop_(&mut self) -> LOOP_W {
1616        LOOP_W { w: self }
1617    }
1618    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1619    #[inline(always)]
1620    pub fn oeta(&mut self) -> OETA_W {
1621        OETA_W { w: self }
1622    }
1623    #[doc = "Bit 19 - Automatic Address matching enable."]
1624    #[inline(always)]
1625    pub fn autoaddr(&mut self) -> AUTOADDR_W {
1626        AUTOADDR_W { w: self }
1627    }
1628    #[doc = "Bit 20 - Output Enable Select."]
1629    #[inline(always)]
1630    pub fn oesel(&mut self) -> OESEL_W {
1631        OESEL_W { w: self }
1632    }
1633    #[doc = "Bit 21 - Output Enable Polarity."]
1634    #[inline(always)]
1635    pub fn oepol(&mut self) -> OEPOL_W {
1636        OEPOL_W { w: self }
1637    }
1638    #[doc = "Bit 22 - Receive data polarity."]
1639    #[inline(always)]
1640    pub fn rxpol(&mut self) -> RXPOL_W {
1641        RXPOL_W { w: self }
1642    }
1643    #[doc = "Bit 23 - Transmit data polarity."]
1644    #[inline(always)]
1645    pub fn txpol(&mut self) -> TXPOL_W {
1646        TXPOL_W { w: self }
1647    }
1648    #[doc = "Writes raw bits to the register."]
1649    #[inline(always)]
1650    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1651        self.0.bits(bits);
1652        self
1653    }
1654}
1655#[doc = "USART Configuration register. Basic USART configuration settings that typically are not changed during operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1656pub struct CFG_SPEC;
1657impl crate::RegisterSpec for CFG_SPEC {
1658    type Ux = u32;
1659}
1660#[doc = "`read()` method returns [cfg::R](R) reader structure"]
1661impl crate::Readable for CFG_SPEC {
1662    type Reader = R;
1663}
1664#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
1665impl crate::Writable for CFG_SPEC {
1666    type Writer = W;
1667}
1668#[doc = "`reset()` method sets CFG to value 0"]
1669impl crate::Resettable for CFG_SPEC {
1670    #[inline(always)]
1671    fn reset_value() -> Self::Ux {
1672        0
1673    }
1674}
lpc55_pac/usart0/cfg.rs

lpc55_pac/usart0/
cfg.rs
