lpc55_pac/syscon/
usb0clkdiv.rs

1#[doc = "Register `USB0CLKDIV` reader"]
2pub struct R(crate::R<USB0CLKDIV_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<USB0CLKDIV_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<USB0CLKDIV_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<USB0CLKDIV_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `USB0CLKDIV` writer"]
17pub struct W(crate::W<USB0CLKDIV_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<USB0CLKDIV_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<USB0CLKDIV_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<USB0CLKDIV_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DIV` reader - Clock divider value."]
38pub struct DIV_R(crate::FieldReader<u8, u8>);
39impl DIV_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u8) -> Self {
42        DIV_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for DIV_R {
46    type Target = crate::FieldReader<u8, u8>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `DIV` writer - Clock divider value."]
53pub struct DIV_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> DIV_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u8) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
61        self.w
62    }
63}
64#[doc = "Resets the divider counter.\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq)]
66pub enum RESET_AW {
67    #[doc = "0: Divider is not reset."]
68    RELEASED = 0,
69    #[doc = "1: Divider is reset."]
70    ASSERTED = 1,
71}
72impl From<RESET_AW> for bool {
73    #[inline(always)]
74    fn from(variant: RESET_AW) -> Self {
75        variant as u8 != 0
76    }
77}
78#[doc = "Field `RESET` writer - Resets the divider counter."]
79pub struct RESET_W<'a> {
80    w: &'a mut W,
81}
82impl<'a> RESET_W<'a> {
83    #[doc = r"Writes `variant` to the field"]
84    #[inline(always)]
85    pub fn variant(self, variant: RESET_AW) -> &'a mut W {
86        self.bit(variant.into())
87    }
88    #[doc = "Divider is not reset."]
89    #[inline(always)]
90    pub fn released(self) -> &'a mut W {
91        self.variant(RESET_AW::RELEASED)
92    }
93    #[doc = "Divider is reset."]
94    #[inline(always)]
95    pub fn asserted(self) -> &'a mut W {
96        self.variant(RESET_AW::ASSERTED)
97    }
98    #[doc = r"Sets the field bit"]
99    #[inline(always)]
100    pub fn set_bit(self) -> &'a mut W {
101        self.bit(true)
102    }
103    #[doc = r"Clears the field bit"]
104    #[inline(always)]
105    pub fn clear_bit(self) -> &'a mut W {
106        self.bit(false)
107    }
108    #[doc = r"Writes raw bits to the field"]
109    #[inline(always)]
110    pub fn bit(self, value: bool) -> &'a mut W {
111        self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
112        self.w
113    }
114}
115#[doc = "Halts the divider counter.\n\nValue on reset: 1"]
116#[derive(Clone, Copy, Debug, PartialEq)]
117pub enum HALT_A {
118    #[doc = "0: Divider clock is running."]
119    RUN = 0,
120    #[doc = "1: Divider clock is stoped."]
121    HALT = 1,
122}
123impl From<HALT_A> for bool {
124    #[inline(always)]
125    fn from(variant: HALT_A) -> Self {
126        variant as u8 != 0
127    }
128}
129#[doc = "Field `HALT` reader - Halts the divider counter."]
130pub struct HALT_R(crate::FieldReader<bool, HALT_A>);
131impl HALT_R {
132    #[inline(always)]
133    pub(crate) fn new(bits: bool) -> Self {
134        HALT_R(crate::FieldReader::new(bits))
135    }
136    #[doc = r"Get enumerated values variant"]
137    #[inline(always)]
138    pub fn variant(&self) -> HALT_A {
139        match self.bits {
140            false => HALT_A::RUN,
141            true => HALT_A::HALT,
142        }
143    }
144    #[doc = "Checks if the value of the field is `RUN`"]
145    #[inline(always)]
146    pub fn is_run(&self) -> bool {
147        **self == HALT_A::RUN
148    }
149    #[doc = "Checks if the value of the field is `HALT`"]
150    #[inline(always)]
151    pub fn is_halt(&self) -> bool {
152        **self == HALT_A::HALT
153    }
154}
155impl core::ops::Deref for HALT_R {
156    type Target = crate::FieldReader<bool, HALT_A>;
157    #[inline(always)]
158    fn deref(&self) -> &Self::Target {
159        &self.0
160    }
161}
162#[doc = "Field `HALT` writer - Halts the divider counter."]
163pub struct HALT_W<'a> {
164    w: &'a mut W,
165}
166impl<'a> HALT_W<'a> {
167    #[doc = r"Writes `variant` to the field"]
168    #[inline(always)]
169    pub fn variant(self, variant: HALT_A) -> &'a mut W {
170        self.bit(variant.into())
171    }
172    #[doc = "Divider clock is running."]
173    #[inline(always)]
174    pub fn run(self) -> &'a mut W {
175        self.variant(HALT_A::RUN)
176    }
177    #[doc = "Divider clock is stoped."]
178    #[inline(always)]
179    pub fn halt(self) -> &'a mut W {
180        self.variant(HALT_A::HALT)
181    }
182    #[doc = r"Sets the field bit"]
183    #[inline(always)]
184    pub fn set_bit(self) -> &'a mut W {
185        self.bit(true)
186    }
187    #[doc = r"Clears the field bit"]
188    #[inline(always)]
189    pub fn clear_bit(self) -> &'a mut W {
190        self.bit(false)
191    }
192    #[doc = r"Writes raw bits to the field"]
193    #[inline(always)]
194    pub fn bit(self, value: bool) -> &'a mut W {
195        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
196        self.w
197    }
198}
199#[doc = "Divider status flag.\n\nValue on reset: 0"]
200#[derive(Clone, Copy, Debug, PartialEq)]
201pub enum REQFLAG_A {
202    #[doc = "0: Divider clock is stable."]
203    STABLE = 0,
204    #[doc = "1: Clock frequency is not stable."]
205    ONGOING = 1,
206}
207impl From<REQFLAG_A> for bool {
208    #[inline(always)]
209    fn from(variant: REQFLAG_A) -> Self {
210        variant as u8 != 0
211    }
212}
213#[doc = "Field `REQFLAG` reader - Divider status flag."]
214pub struct REQFLAG_R(crate::FieldReader<bool, REQFLAG_A>);
215impl REQFLAG_R {
216    #[inline(always)]
217    pub(crate) fn new(bits: bool) -> Self {
218        REQFLAG_R(crate::FieldReader::new(bits))
219    }
220    #[doc = r"Get enumerated values variant"]
221    #[inline(always)]
222    pub fn variant(&self) -> REQFLAG_A {
223        match self.bits {
224            false => REQFLAG_A::STABLE,
225            true => REQFLAG_A::ONGOING,
226        }
227    }
228    #[doc = "Checks if the value of the field is `STABLE`"]
229    #[inline(always)]
230    pub fn is_stable(&self) -> bool {
231        **self == REQFLAG_A::STABLE
232    }
233    #[doc = "Checks if the value of the field is `ONGOING`"]
234    #[inline(always)]
235    pub fn is_ongoing(&self) -> bool {
236        **self == REQFLAG_A::ONGOING
237    }
238}
239impl core::ops::Deref for REQFLAG_R {
240    type Target = crate::FieldReader<bool, REQFLAG_A>;
241    #[inline(always)]
242    fn deref(&self) -> &Self::Target {
243        &self.0
244    }
245}
246impl R {
247    #[doc = "Bits 0:7 - Clock divider value."]
248    #[inline(always)]
249    pub fn div(&self) -> DIV_R {
250        DIV_R::new((self.bits & 0xff) as u8)
251    }
252    #[doc = "Bit 30 - Halts the divider counter."]
253    #[inline(always)]
254    pub fn halt(&self) -> HALT_R {
255        HALT_R::new(((self.bits >> 30) & 0x01) != 0)
256    }
257    #[doc = "Bit 31 - Divider status flag."]
258    #[inline(always)]
259    pub fn reqflag(&self) -> REQFLAG_R {
260        REQFLAG_R::new(((self.bits >> 31) & 0x01) != 0)
261    }
262}
263impl W {
264    #[doc = "Bits 0:7 - Clock divider value."]
265    #[inline(always)]
266    pub fn div(&mut self) -> DIV_W {
267        DIV_W { w: self }
268    }
269    #[doc = "Bit 29 - Resets the divider counter."]
270    #[inline(always)]
271    pub fn reset(&mut self) -> RESET_W {
272        RESET_W { w: self }
273    }
274    #[doc = "Bit 30 - Halts the divider counter."]
275    #[inline(always)]
276    pub fn halt(&mut self) -> HALT_W {
277        HALT_W { w: self }
278    }
279    #[doc = "Writes raw bits to the register."]
280    #[inline(always)]
281    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
282        self.0.bits(bits);
283        self
284    }
285}
286#[doc = "USB0 Clock divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb0clkdiv](index.html) module"]
287pub struct USB0CLKDIV_SPEC;
288impl crate::RegisterSpec for USB0CLKDIV_SPEC {
289    type Ux = u32;
290}
291#[doc = "`read()` method returns [usb0clkdiv::R](R) reader structure"]
292impl crate::Readable for USB0CLKDIV_SPEC {
293    type Reader = R;
294}
295#[doc = "`write(|w| ..)` method takes [usb0clkdiv::W](W) writer structure"]
296impl crate::Writable for USB0CLKDIV_SPEC {
297    type Writer = W;
298}
299#[doc = "`reset()` method sets USB0CLKDIV to value 0x4000_0000"]
300impl crate::Resettable for USB0CLKDIV_SPEC {
301    #[inline(always)]
302    fn reset_value() -> Self::Ux {
303        0x4000_0000
304    }
305}
lpc55_pac/syscon/usb0clkdiv.rs

lpc55_pac/syscon/
usb0clkdiv.rs
