lpc55_pac/syscon/
gpiopsync.rs

1#[doc = "Register `GPIOPSYNC` reader"]
2pub struct R(crate::R<GPIOPSYNC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GPIOPSYNC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GPIOPSYNC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GPIOPSYNC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GPIOPSYNC` writer"]
17pub struct W(crate::W<GPIOPSYNC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GPIOPSYNC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GPIOPSYNC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GPIOPSYNC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Enable bypass of the first stage of synchonization inside GPIO_INT module.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum PSYNC_A {
40    #[doc = "0: use the first stage of synchonization inside GPIO_INT module."]
41    USED = 0,
42    #[doc = "1: bypass of the first stage of synchonization inside GPIO_INT module."]
43    BYPASS = 1,
44}
45impl From<PSYNC_A> for bool {
46    #[inline(always)]
47    fn from(variant: PSYNC_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `PSYNC` reader - Enable bypass of the first stage of synchonization inside GPIO_INT module."]
52pub struct PSYNC_R(crate::FieldReader<bool, PSYNC_A>);
53impl PSYNC_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        PSYNC_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> PSYNC_A {
61        match self.bits {
62            false => PSYNC_A::USED,
63            true => PSYNC_A::BYPASS,
64        }
65    }
66    #[doc = "Checks if the value of the field is `USED`"]
67    #[inline(always)]
68    pub fn is_used(&self) -> bool {
69        **self == PSYNC_A::USED
70    }
71    #[doc = "Checks if the value of the field is `BYPASS`"]
72    #[inline(always)]
73    pub fn is_bypass(&self) -> bool {
74        **self == PSYNC_A::BYPASS
75    }
76}
77impl core::ops::Deref for PSYNC_R {
78    type Target = crate::FieldReader<bool, PSYNC_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `PSYNC` writer - Enable bypass of the first stage of synchonization inside GPIO_INT module."]
85pub struct PSYNC_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> PSYNC_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: PSYNC_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "use the first stage of synchonization inside GPIO_INT module."]
95    #[inline(always)]
96    pub fn used(self) -> &'a mut W {
97        self.variant(PSYNC_A::USED)
98    }
99    #[doc = "bypass of the first stage of synchonization inside GPIO_INT module."]
100    #[inline(always)]
101    pub fn bypass(self) -> &'a mut W {
102        self.variant(PSYNC_A::BYPASS)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121impl R {
122    #[doc = "Bit 0 - Enable bypass of the first stage of synchonization inside GPIO_INT module."]
123    #[inline(always)]
124    pub fn psync(&self) -> PSYNC_R {
125        PSYNC_R::new((self.bits & 0x01) != 0)
126    }
127}
128impl W {
129    #[doc = "Bit 0 - Enable bypass of the first stage of synchonization inside GPIO_INT module."]
130    #[inline(always)]
131    pub fn psync(&mut self) -> PSYNC_W {
132        PSYNC_W { w: self }
133    }
134    #[doc = "Writes raw bits to the register."]
135    #[inline(always)]
136    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
137        self.0.bits(bits);
138        self
139    }
140}
141#[doc = "Enable bypass of the first stage of synchonization inside GPIO_INT module\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpiopsync](index.html) module"]
142pub struct GPIOPSYNC_SPEC;
143impl crate::RegisterSpec for GPIOPSYNC_SPEC {
144    type Ux = u32;
145}
146#[doc = "`read()` method returns [gpiopsync::R](R) reader structure"]
147impl crate::Readable for GPIOPSYNC_SPEC {
148    type Reader = R;
149}
150#[doc = "`write(|w| ..)` method takes [gpiopsync::W](W) writer structure"]
151impl crate::Writable for GPIOPSYNC_SPEC {
152    type Writer = W;
153}
154#[doc = "`reset()` method sets GPIOPSYNC to value 0"]
155impl crate::Resettable for GPIOPSYNC_SPEC {
156    #[inline(always)]
157    fn reset_value() -> Self::Ux {
158        0
159    }
160}
lpc55_pac/syscon/gpiopsync.rs

lpc55_pac/syscon/
gpiopsync.rs
