lpc55_pac/syscon/
fcclksel5.rs

1#[doc = "Register `FCCLKSEL5` reader"]
2pub struct R(crate::R<FCCLKSEL5_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FCCLKSEL5_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FCCLKSEL5_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FCCLKSEL5_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FCCLKSEL5` writer"]
17pub struct W(crate::W<FCCLKSEL5_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FCCLKSEL5_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FCCLKSEL5_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FCCLKSEL5_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Flexcomm Interface 5 clock source select for Fractional Rate Divider.\n\nValue on reset: 7"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum SEL_A {
41    #[doc = "0: Main clock."]
42    ENUM_0X0 = 0,
43    #[doc = "1: system PLL divided clock."]
44    ENUM_0X1 = 1,
45    #[doc = "2: FRO 12 MHz clock."]
46    ENUM_0X2 = 2,
47    #[doc = "3: FRO 96 MHz clock."]
48    ENUM_0X3 = 3,
49    #[doc = "4: FRO 1MHz clock."]
50    ENUM_0X4 = 4,
51    #[doc = "5: MCLK clock."]
52    ENUM_0X5 = 5,
53    #[doc = "6: Oscillator 32 kHz clock."]
54    ENUM_0X6 = 6,
55    #[doc = "7: No clock."]
56    ENUM_0X7 = 7,
57}
58impl From<SEL_A> for u8 {
59    #[inline(always)]
60    fn from(variant: SEL_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `SEL` reader - Flexcomm Interface 5 clock source select for Fractional Rate Divider."]
65pub struct SEL_R(crate::FieldReader<u8, SEL_A>);
66impl SEL_R {
67    #[inline(always)]
68    pub(crate) fn new(bits: u8) -> Self {
69        SEL_R(crate::FieldReader::new(bits))
70    }
71    #[doc = r"Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> SEL_A {
74        match self.bits {
75            0 => SEL_A::ENUM_0X0,
76            1 => SEL_A::ENUM_0X1,
77            2 => SEL_A::ENUM_0X2,
78            3 => SEL_A::ENUM_0X3,
79            4 => SEL_A::ENUM_0X4,
80            5 => SEL_A::ENUM_0X5,
81            6 => SEL_A::ENUM_0X6,
82            7 => SEL_A::ENUM_0X7,
83            _ => unreachable!(),
84        }
85    }
86    #[doc = "Checks if the value of the field is `ENUM_0X0`"]
87    #[inline(always)]
88    pub fn is_enum_0x0(&self) -> bool {
89        **self == SEL_A::ENUM_0X0
90    }
91    #[doc = "Checks if the value of the field is `ENUM_0X1`"]
92    #[inline(always)]
93    pub fn is_enum_0x1(&self) -> bool {
94        **self == SEL_A::ENUM_0X1
95    }
96    #[doc = "Checks if the value of the field is `ENUM_0X2`"]
97    #[inline(always)]
98    pub fn is_enum_0x2(&self) -> bool {
99        **self == SEL_A::ENUM_0X2
100    }
101    #[doc = "Checks if the value of the field is `ENUM_0X3`"]
102    #[inline(always)]
103    pub fn is_enum_0x3(&self) -> bool {
104        **self == SEL_A::ENUM_0X3
105    }
106    #[doc = "Checks if the value of the field is `ENUM_0X4`"]
107    #[inline(always)]
108    pub fn is_enum_0x4(&self) -> bool {
109        **self == SEL_A::ENUM_0X4
110    }
111    #[doc = "Checks if the value of the field is `ENUM_0X5`"]
112    #[inline(always)]
113    pub fn is_enum_0x5(&self) -> bool {
114        **self == SEL_A::ENUM_0X5
115    }
116    #[doc = "Checks if the value of the field is `ENUM_0X6`"]
117    #[inline(always)]
118    pub fn is_enum_0x6(&self) -> bool {
119        **self == SEL_A::ENUM_0X6
120    }
121    #[doc = "Checks if the value of the field is `ENUM_0X7`"]
122    #[inline(always)]
123    pub fn is_enum_0x7(&self) -> bool {
124        **self == SEL_A::ENUM_0X7
125    }
126}
127impl core::ops::Deref for SEL_R {
128    type Target = crate::FieldReader<u8, SEL_A>;
129    #[inline(always)]
130    fn deref(&self) -> &Self::Target {
131        &self.0
132    }
133}
134#[doc = "Field `SEL` writer - Flexcomm Interface 5 clock source select for Fractional Rate Divider."]
135pub struct SEL_W<'a> {
136    w: &'a mut W,
137}
138impl<'a> SEL_W<'a> {
139    #[doc = r"Writes `variant` to the field"]
140    #[inline(always)]
141    pub fn variant(self, variant: SEL_A) -> &'a mut W {
142        self.bits(variant.into())
143    }
144    #[doc = "Main clock."]
145    #[inline(always)]
146    pub fn enum_0x0(self) -> &'a mut W {
147        self.variant(SEL_A::ENUM_0X0)
148    }
149    #[doc = "system PLL divided clock."]
150    #[inline(always)]
151    pub fn enum_0x1(self) -> &'a mut W {
152        self.variant(SEL_A::ENUM_0X1)
153    }
154    #[doc = "FRO 12 MHz clock."]
155    #[inline(always)]
156    pub fn enum_0x2(self) -> &'a mut W {
157        self.variant(SEL_A::ENUM_0X2)
158    }
159    #[doc = "FRO 96 MHz clock."]
160    #[inline(always)]
161    pub fn enum_0x3(self) -> &'a mut W {
162        self.variant(SEL_A::ENUM_0X3)
163    }
164    #[doc = "FRO 1MHz clock."]
165    #[inline(always)]
166    pub fn enum_0x4(self) -> &'a mut W {
167        self.variant(SEL_A::ENUM_0X4)
168    }
169    #[doc = "MCLK clock."]
170    #[inline(always)]
171    pub fn enum_0x5(self) -> &'a mut W {
172        self.variant(SEL_A::ENUM_0X5)
173    }
174    #[doc = "Oscillator 32 kHz clock."]
175    #[inline(always)]
176    pub fn enum_0x6(self) -> &'a mut W {
177        self.variant(SEL_A::ENUM_0X6)
178    }
179    #[doc = "No clock."]
180    #[inline(always)]
181    pub fn enum_0x7(self) -> &'a mut W {
182        self.variant(SEL_A::ENUM_0X7)
183    }
184    #[doc = r"Writes raw bits to the field"]
185    #[inline(always)]
186    pub fn bits(self, value: u8) -> &'a mut W {
187        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
188        self.w
189    }
190}
191impl R {
192    #[doc = "Bits 0:2 - Flexcomm Interface 5 clock source select for Fractional Rate Divider."]
193    #[inline(always)]
194    pub fn sel(&self) -> SEL_R {
195        SEL_R::new((self.bits & 0x07) as u8)
196    }
197}
198impl W {
199    #[doc = "Bits 0:2 - Flexcomm Interface 5 clock source select for Fractional Rate Divider."]
200    #[inline(always)]
201    pub fn sel(&mut self) -> SEL_W {
202        SEL_W { w: self }
203    }
204    #[doc = "Writes raw bits to the register."]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.0.bits(bits);
208        self
209    }
210}
211#[doc = "Flexcomm Interface 5 clock source select for Fractional Rate Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcclksel5](index.html) module"]
212pub struct FCCLKSEL5_SPEC;
213impl crate::RegisterSpec for FCCLKSEL5_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [fcclksel5::R](R) reader structure"]
217impl crate::Readable for FCCLKSEL5_SPEC {
218    type Reader = R;
219}
220#[doc = "`write(|w| ..)` method takes [fcclksel5::W](W) writer structure"]
221impl crate::Writable for FCCLKSEL5_SPEC {
222    type Writer = W;
223}
224#[doc = "`reset()` method sets FCCLKSEL5 to value 0x07"]
225impl crate::Resettable for FCCLKSEL5_SPEC {
226    #[inline(always)]
227    fn reset_value() -> Self::Ux {
228        0x07
229    }
230}
lpc55_pac/syscon/fcclksel5.rs

lpc55_pac/syscon/
fcclksel5.rs
