1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Memory Remap control register"]
5 pub memoryremap: crate::Reg<memoryremap::MEMORYREMAP_SPEC>,
6 _reserved1: [u8; 0x0c],
7 #[doc = "0x10 - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest"]
8 pub ahbmatprio: crate::Reg<ahbmatprio::AHBMATPRIO_SPEC>,
9 _reserved2: [u8; 0x24],
10 #[doc = "0x38 - System tick calibration for secure part of CPU0"]
11 pub cpu0stckcal: crate::Reg<cpu0stckcal::CPU0STCKCAL_SPEC>,
12 #[doc = "0x3c - System tick calibration for non-secure part of CPU0"]
13 pub cpu0nstckcal: crate::Reg<cpu0nstckcal::CPU0NSTCKCAL_SPEC>,
14 #[doc = "0x40 - System tick calibration for CPU1"]
15 pub cpu1stckcal: crate::Reg<cpu1stckcal::CPU1STCKCAL_SPEC>,
16 _reserved5: [u8; 0x04],
17 #[doc = "0x48 - NMI Source Select"]
18 pub nmisrc: crate::Reg<nmisrc::NMISRC_SPEC>,
19 _reserved6: [u8; 0xb4],
20 #[doc = "0x100 - Peripheral reset control 0"]
21 pub presetctrl0: crate::Reg<presetctrl0::PRESETCTRL0_SPEC>,
22 #[doc = "0x104 - Peripheral reset control 1"]
23 pub presetctrl1: crate::Reg<presetctrl1::PRESETCTRL1_SPEC>,
24 #[doc = "0x108 - Peripheral reset control 2"]
25 pub presetctrl2: crate::Reg<presetctrl2::PRESETCTRL2_SPEC>,
26 _reserved9: [u8; 0x14],
27 #[doc = "0x120..0x12c - Peripheral reset control set register"]
28 pub presetctrlset: [crate::Reg<presetctrlset::PRESETCTRLSET_SPEC>; 3],
29 _reserved10: [u8; 0x14],
30 #[doc = "0x140..0x14c - Peripheral reset control clear register"]
31 pub presetctrlclr: [crate::Reg<presetctrlclr::PRESETCTRLCLR_SPEC>; 3],
32 _reserved11: [u8; 0x14],
33 #[doc = "0x160 - generate a software_reset"]
34 pub swr_reset: crate::Reg<swr_reset::SWR_RESET_SPEC>,
35 _reserved12: [u8; 0x9c],
36 #[doc = "0x200 - AHB Clock control 0"]
37 pub ahbclkctrl0: crate::Reg<ahbclkctrl0::AHBCLKCTRL0_SPEC>,
38 #[doc = "0x204 - AHB Clock control 1"]
39 pub ahbclkctrl1: crate::Reg<ahbclkctrl1::AHBCLKCTRL1_SPEC>,
40 #[doc = "0x208 - AHB Clock control 2"]
41 pub ahbclkctrl2: crate::Reg<ahbclkctrl2::AHBCLKCTRL2_SPEC>,
42 _reserved15: [u8; 0x14],
43 #[doc = "0x220..0x22c - Peripheral reset control register"]
44 pub ahbclkctrlset: [crate::Reg<ahbclkctrlset::AHBCLKCTRLSET_SPEC>; 3],
45 _reserved16: [u8; 0x14],
46 #[doc = "0x240..0x24c - Peripheral reset control register"]
47 pub ahbclkctrlclr: [crate::Reg<ahbclkctrlclr::AHBCLKCTRLCLR_SPEC>; 3],
48 _reserved17: [u8; 0x14],
49 _reserved_17_systickclksel0: [u8; 0x04],
50 _reserved_18_systickclksel1: [u8; 0x04],
51 #[doc = "0x268 - Trace clock source select"]
52 pub traceclksel: crate::Reg<traceclksel::TRACECLKSEL_SPEC>,
53 _reserved_20_ctimerclksel0: [u8; 0x04],
54 _reserved_21_ctimerclksel1: [u8; 0x04],
55 _reserved_22_ctimerclksel2: [u8; 0x04],
56 _reserved_23_ctimerclksel3: [u8; 0x04],
57 _reserved_24_ctimerclksel4: [u8; 0x04],
58 #[doc = "0x280 - Main clock A source select"]
59 pub mainclksela: crate::Reg<mainclksela::MAINCLKSELA_SPEC>,
60 #[doc = "0x284 - Main clock source select"]
61 pub mainclkselb: crate::Reg<mainclkselb::MAINCLKSELB_SPEC>,
62 #[doc = "0x288 - CLKOUT clock source select"]
63 pub clkoutsel: crate::Reg<clkoutsel::CLKOUTSEL_SPEC>,
64 _reserved28: [u8; 0x04],
65 #[doc = "0x290 - PLL0 clock source select"]
66 pub pll0clksel: crate::Reg<pll0clksel::PLL0CLKSEL_SPEC>,
67 #[doc = "0x294 - PLL1 clock source select"]
68 pub pll1clksel: crate::Reg<pll1clksel::PLL1CLKSEL_SPEC>,
69 _reserved30: [u8; 0x0c],
70 #[doc = "0x2a4 - ADC clock source select"]
71 pub adcclksel: crate::Reg<adcclksel::ADCCLKSEL_SPEC>,
72 #[doc = "0x2a8 - FS USB clock source select"]
73 pub usb0clksel: crate::Reg<usb0clksel::USB0CLKSEL_SPEC>,
74 _reserved32: [u8; 0x04],
75 _reserved_32_fcclksel0: [u8; 0x04],
76 _reserved_33_fcclksel1: [u8; 0x04],
77 _reserved_34_fcclksel2: [u8; 0x04],
78 _reserved_35_fcclksel3: [u8; 0x04],
79 _reserved_36_fcclksel4: [u8; 0x04],
80 _reserved_37_fcclksel5: [u8; 0x04],
81 _reserved_38_fcclksel6: [u8; 0x04],
82 _reserved_39_fcclksel7: [u8; 0x04],
83 #[doc = "0x2d0 - HS LSPI clock source select"]
84 pub hslspiclksel: crate::Reg<hslspiclksel::HSLSPICLKSEL_SPEC>,
85 _reserved41: [u8; 0x0c],
86 #[doc = "0x2e0 - MCLK clock source select"]
87 pub mclkclksel: crate::Reg<mclkclksel::MCLKCLKSEL_SPEC>,
88 _reserved42: [u8; 0x0c],
89 #[doc = "0x2f0 - SCTimer/PWM clock source select"]
90 pub sctclksel: crate::Reg<sctclksel::SCTCLKSEL_SPEC>,
91 _reserved43: [u8; 0x04],
92 #[doc = "0x2f8 - SDIO clock source select"]
93 pub sdioclksel: crate::Reg<sdioclksel::SDIOCLKSEL_SPEC>,
94 _reserved44: [u8; 0x04],
95 #[doc = "0x300 - System Tick Timer divider for CPU0"]
96 pub systickclkdiv0: crate::Reg<systickclkdiv0::SYSTICKCLKDIV0_SPEC>,
97 #[doc = "0x304 - System Tick Timer divider for CPU1"]
98 pub systickclkdiv1: crate::Reg<systickclkdiv1::SYSTICKCLKDIV1_SPEC>,
99 #[doc = "0x308 - TRACE clock divider"]
100 pub traceclkdiv: crate::Reg<traceclkdiv::TRACECLKDIV_SPEC>,
101 _reserved47: [u8; 0x14],
102 _reserved_47_flexfrg0ctrl: [u8; 0x04],
103 _reserved_48_flexfrg1ctrl: [u8; 0x04],
104 _reserved_49_flexfrg2ctrl: [u8; 0x04],
105 _reserved_50_flexfrg3ctrl: [u8; 0x04],
106 _reserved_51_flexfrg4ctrl: [u8; 0x04],
107 _reserved_52_flexfrg5ctrl: [u8; 0x04],
108 _reserved_53_flexfrg6ctrl: [u8; 0x04],
109 _reserved_54_flexfrg7ctrl: [u8; 0x04],
110 _reserved55: [u8; 0x40],
111 #[doc = "0x380 - System clock divider"]
112 pub ahbclkdiv: crate::Reg<ahbclkdiv::AHBCLKDIV_SPEC>,
113 #[doc = "0x384 - CLKOUT clock divider"]
114 pub clkoutdiv: crate::Reg<clkoutdiv::CLKOUTDIV_SPEC>,
115 #[doc = "0x388 - FRO_HF (96MHz) clock divider"]
116 pub frohfdiv: crate::Reg<frohfdiv::FROHFDIV_SPEC>,
117 #[doc = "0x38c - WDT clock divider"]
118 pub wdtclkdiv: crate::Reg<wdtclkdiv::WDTCLKDIV_SPEC>,
119 _reserved59: [u8; 0x04],
120 #[doc = "0x394 - ADC clock divider"]
121 pub adcclkdiv: crate::Reg<adcclkdiv::ADCCLKDIV_SPEC>,
122 #[doc = "0x398 - USB0 Clock divider"]
123 pub usb0clkdiv: crate::Reg<usb0clkdiv::USB0CLKDIV_SPEC>,
124 _reserved61: [u8; 0x10],
125 #[doc = "0x3ac - I2S MCLK clock divider"]
126 pub mclkdiv: crate::Reg<mclkdiv::MCLKDIV_SPEC>,
127 _reserved62: [u8; 0x04],
128 #[doc = "0x3b4 - SCT/PWM clock divider"]
129 pub sctclkdiv: crate::Reg<sctclkdiv::SCTCLKDIV_SPEC>,
130 _reserved63: [u8; 0x04],
131 #[doc = "0x3bc - SDIO clock divider"]
132 pub sdioclkdiv: crate::Reg<sdioclkdiv::SDIOCLKDIV_SPEC>,
133 _reserved64: [u8; 0x04],
134 #[doc = "0x3c4 - PLL0 clock divider"]
135 pub pll0clkdiv: crate::Reg<pll0clkdiv::PLL0CLKDIV_SPEC>,
136 _reserved65: [u8; 0x34],
137 #[doc = "0x3fc - Control clock configuration registers access (like xxxDIV, xxxSEL)"]
138 pub clockgenupdatelockout: crate::Reg<clockgenupdatelockout::CLOCKGENUPDATELOCKOUT_SPEC>,
139 #[doc = "0x400 - FMC configuration register"]
140 pub fmccr: crate::Reg<fmccr::FMCCR_SPEC>,
141 _reserved67: [u8; 0x08],
142 #[doc = "0x40c - USB0 need clock control"]
143 pub usb0needclkctrl: crate::Reg<usb0needclkctrl::USB0NEEDCLKCTRL_SPEC>,
144 #[doc = "0x410 - USB0 need clock status"]
145 pub usb0needclkstat: crate::Reg<usb0needclkstat::USB0NEEDCLKSTAT_SPEC>,
146 _reserved69: [u8; 0x08],
147 #[doc = "0x41c - FMCflush control"]
148 pub fmcflush: crate::Reg<fmcflush::FMCFLUSH_SPEC>,
149 #[doc = "0x420 - MCLK control"]
150 pub mclkio: crate::Reg<mclkio::MCLKIO_SPEC>,
151 #[doc = "0x424 - USB1 need clock control"]
152 pub usb1needclkctrl: crate::Reg<usb1needclkctrl::USB1NEEDCLKCTRL_SPEC>,
153 #[doc = "0x428 - USB1 need clock status"]
154 pub usb1needclkstat: crate::Reg<usb1needclkstat::USB1NEEDCLKSTAT_SPEC>,
155 _reserved73: [u8; 0x34],
156 #[doc = "0x460 - SDIO CCLKIN phase and delay control"]
157 pub sdioclkctrl: crate::Reg<sdioclkctrl::SDIOCLKCTRL_SPEC>,
158 _reserved74: [u8; 0xfc],
159 #[doc = "0x560 - PLL1 550m control"]
160 pub pll1ctrl: crate::Reg<pll1ctrl::PLL1CTRL_SPEC>,
161 #[doc = "0x564 - PLL1 550m status"]
162 pub pll1stat: crate::Reg<pll1stat::PLL1STAT_SPEC>,
163 #[doc = "0x568 - PLL1 550m N divider"]
164 pub pll1ndec: crate::Reg<pll1ndec::PLL1NDEC_SPEC>,
165 #[doc = "0x56c - PLL1 550m M divider"]
166 pub pll1mdec: crate::Reg<pll1mdec::PLL1MDEC_SPEC>,
167 #[doc = "0x570 - PLL1 550m P divider"]
168 pub pll1pdec: crate::Reg<pll1pdec::PLL1PDEC_SPEC>,
169 _reserved79: [u8; 0x0c],
170 #[doc = "0x580 - PLL0 550m control"]
171 pub pll0ctrl: crate::Reg<pll0ctrl::PLL0CTRL_SPEC>,
172 #[doc = "0x584 - PLL0 550m status"]
173 pub pll0stat: crate::Reg<pll0stat::PLL0STAT_SPEC>,
174 #[doc = "0x588 - PLL0 550m N divider"]
175 pub pll0ndec: crate::Reg<pll0ndec::PLL0NDEC_SPEC>,
176 #[doc = "0x58c - PLL0 550m P divider"]
177 pub pll0pdec: crate::Reg<pll0pdec::PLL0PDEC_SPEC>,
178 #[doc = "0x590 - PLL0 Spread Spectrum Wrapper control register 0"]
179 pub pll0sscg0: crate::Reg<pll0sscg0::PLL0SSCG0_SPEC>,
180 #[doc = "0x594 - PLL0 Spread Spectrum Wrapper control register 1"]
181 pub pll0sscg1: crate::Reg<pll0sscg1::PLL0SSCG1_SPEC>,
182 _reserved85: [u8; 0x0268],
183 #[doc = "0x800 - CPU Control for multiple processors"]
184 pub cpuctrl: crate::Reg<cpuctrl::CPUCTRL_SPEC>,
185 #[doc = "0x804 - Coprocessor Boot Address"]
186 pub cpboot: crate::Reg<cpboot::CPBOOT_SPEC>,
187 _reserved87: [u8; 0x04],
188 #[doc = "0x80c - CPU Status"]
189 pub cpstat: crate::Reg<cpstat::CPSTAT_SPEC>,
190 _reserved88: [u8; 0x0208],
191 #[doc = "0xa18 - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures"]
192 pub clock_ctrl: crate::Reg<clock_ctrl::CLOCK_CTRL_SPEC>,
193 _reserved89: [u8; 0xf4],
194 #[doc = "0xb10 - Comparator Interrupt control"]
195 pub comp_int_ctrl: crate::Reg<comp_int_ctrl::COMP_INT_CTRL_SPEC>,
196 #[doc = "0xb14 - Comparator Interrupt status"]
197 pub comp_int_status: crate::Reg<comp_int_status::COMP_INT_STATUS_SPEC>,
198 _reserved91: [u8; 0x02ec],
199 #[doc = "0xe04 - Control automatic clock gating"]
200 pub autoclkgateoverride: crate::Reg<autoclkgateoverride::AUTOCLKGATEOVERRIDE_SPEC>,
201 #[doc = "0xe08 - Enable bypass of the first stage of synchonization inside GPIO_INT module"]
202 pub gpiopsync: crate::Reg<gpiopsync::GPIOPSYNC_SPEC>,
203 _reserved93: [u8; 0x0194],
204 #[doc = "0xfa0 - Control write access to security registers."]
205 pub debug_lock_en: crate::Reg<debug_lock_en::DEBUG_LOCK_EN_SPEC>,
206 #[doc = "0xfa4 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control."]
207 pub debug_features: crate::Reg<debug_features::DEBUG_FEATURES_SPEC>,
208 #[doc = "0xfa8 - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register."]
209 pub debug_features_dp: crate::Reg<debug_features_dp::DEBUG_FEATURES_DP_SPEC>,
210 _reserved96: [u8; 0x10],
211 #[doc = "0xfbc - block quiddikey/PUF all index."]
212 pub key_block: crate::Reg<key_block::KEY_BLOCK_SPEC>,
213 #[doc = "0xfc0 - Debug authentication BEACON register"]
214 pub debug_auth_beacon: crate::Reg<debug_auth_beacon::DEBUG_AUTH_BEACON_SPEC>,
215 _reserved98: [u8; 0x10],
216 #[doc = "0xfd4 - CPUs configuration register"]
217 pub cpucfg: crate::Reg<cpucfg::CPUCFG_SPEC>,
218 _reserved99: [u8; 0x20],
219 #[doc = "0xff8 - Device ID"]
220 pub device_id0: crate::Reg<device_id0::DEVICE_ID0_SPEC>,
221 #[doc = "0xffc - Chip revision ID and Number"]
222 pub dieid: crate::Reg<dieid::DIEID_SPEC>,
223}
224impl RegisterBlock {
225 #[doc = "0x260 - Peripheral reset control register"]
226 #[inline(always)]
227 pub fn systickclkselx0(&self) -> &crate::Reg<systickclkselx0::SYSTICKCLKSELX0_SPEC> {
228 unsafe {
229 &*(((self as *const Self) as *const u8).add(608usize)
230 as *const crate::Reg<systickclkselx0::SYSTICKCLKSELX0_SPEC>)
231 }
232 }
233 #[doc = "0x260 - System Tick Timer for CPU0 source select"]
234 #[inline(always)]
235 pub fn systickclksel0(&self) -> &crate::Reg<systickclksel0::SYSTICKCLKSEL0_SPEC> {
236 unsafe {
237 &*(((self as *const Self) as *const u8).add(608usize)
238 as *const crate::Reg<systickclksel0::SYSTICKCLKSEL0_SPEC>)
239 }
240 }
241 #[doc = "0x264 - Peripheral reset control register"]
242 #[inline(always)]
243 pub fn systickclkselx1(&self) -> &crate::Reg<systickclkselx1::SYSTICKCLKSELX1_SPEC> {
244 unsafe {
245 &*(((self as *const Self) as *const u8).add(612usize)
246 as *const crate::Reg<systickclkselx1::SYSTICKCLKSELX1_SPEC>)
247 }
248 }
249 #[doc = "0x264 - System Tick Timer for CPU1 source select"]
250 #[inline(always)]
251 pub fn systickclksel1(&self) -> &crate::Reg<systickclksel1::SYSTICKCLKSEL1_SPEC> {
252 unsafe {
253 &*(((self as *const Self) as *const u8).add(612usize)
254 as *const crate::Reg<systickclksel1::SYSTICKCLKSEL1_SPEC>)
255 }
256 }
257 #[doc = "0x26c - Peripheral reset control register"]
258 #[inline(always)]
259 pub fn ctimerclkselx0(&self) -> &crate::Reg<ctimerclkselx0::CTIMERCLKSELX0_SPEC> {
260 unsafe {
261 &*(((self as *const Self) as *const u8).add(620usize)
262 as *const crate::Reg<ctimerclkselx0::CTIMERCLKSELX0_SPEC>)
263 }
264 }
265 #[doc = "0x26c - CTimer 0 clock source select"]
266 #[inline(always)]
267 pub fn ctimerclksel0(&self) -> &crate::Reg<ctimerclksel0::CTIMERCLKSEL0_SPEC> {
268 unsafe {
269 &*(((self as *const Self) as *const u8).add(620usize)
270 as *const crate::Reg<ctimerclksel0::CTIMERCLKSEL0_SPEC>)
271 }
272 }
273 #[doc = "0x270 - Peripheral reset control register"]
274 #[inline(always)]
275 pub fn ctimerclkselx1(&self) -> &crate::Reg<ctimerclkselx1::CTIMERCLKSELX1_SPEC> {
276 unsafe {
277 &*(((self as *const Self) as *const u8).add(624usize)
278 as *const crate::Reg<ctimerclkselx1::CTIMERCLKSELX1_SPEC>)
279 }
280 }
281 #[doc = "0x270 - CTimer 1 clock source select"]
282 #[inline(always)]
283 pub fn ctimerclksel1(&self) -> &crate::Reg<ctimerclksel1::CTIMERCLKSEL1_SPEC> {
284 unsafe {
285 &*(((self as *const Self) as *const u8).add(624usize)
286 as *const crate::Reg<ctimerclksel1::CTIMERCLKSEL1_SPEC>)
287 }
288 }
289 #[doc = "0x274 - Peripheral reset control register"]
290 #[inline(always)]
291 pub fn ctimerclkselx2(&self) -> &crate::Reg<ctimerclkselx2::CTIMERCLKSELX2_SPEC> {
292 unsafe {
293 &*(((self as *const Self) as *const u8).add(628usize)
294 as *const crate::Reg<ctimerclkselx2::CTIMERCLKSELX2_SPEC>)
295 }
296 }
297 #[doc = "0x274 - CTimer 2 clock source select"]
298 #[inline(always)]
299 pub fn ctimerclksel2(&self) -> &crate::Reg<ctimerclksel2::CTIMERCLKSEL2_SPEC> {
300 unsafe {
301 &*(((self as *const Self) as *const u8).add(628usize)
302 as *const crate::Reg<ctimerclksel2::CTIMERCLKSEL2_SPEC>)
303 }
304 }
305 #[doc = "0x278 - Peripheral reset control register"]
306 #[inline(always)]
307 pub fn ctimerclkselx3(&self) -> &crate::Reg<ctimerclkselx3::CTIMERCLKSELX3_SPEC> {
308 unsafe {
309 &*(((self as *const Self) as *const u8).add(632usize)
310 as *const crate::Reg<ctimerclkselx3::CTIMERCLKSELX3_SPEC>)
311 }
312 }
313 #[doc = "0x278 - CTimer 3 clock source select"]
314 #[inline(always)]
315 pub fn ctimerclksel3(&self) -> &crate::Reg<ctimerclksel3::CTIMERCLKSEL3_SPEC> {
316 unsafe {
317 &*(((self as *const Self) as *const u8).add(632usize)
318 as *const crate::Reg<ctimerclksel3::CTIMERCLKSEL3_SPEC>)
319 }
320 }
321 #[doc = "0x27c - Peripheral reset control register"]
322 #[inline(always)]
323 pub fn ctimerclkselx4(&self) -> &crate::Reg<ctimerclkselx4::CTIMERCLKSELX4_SPEC> {
324 unsafe {
325 &*(((self as *const Self) as *const u8).add(636usize)
326 as *const crate::Reg<ctimerclkselx4::CTIMERCLKSELX4_SPEC>)
327 }
328 }
329 #[doc = "0x27c - CTimer 4 clock source select"]
330 #[inline(always)]
331 pub fn ctimerclksel4(&self) -> &crate::Reg<ctimerclksel4::CTIMERCLKSEL4_SPEC> {
332 unsafe {
333 &*(((self as *const Self) as *const u8).add(636usize)
334 as *const crate::Reg<ctimerclksel4::CTIMERCLKSEL4_SPEC>)
335 }
336 }
337 #[doc = "0x2b0 - Peripheral reset control register"]
338 #[inline(always)]
339 pub fn fcclkselx0(&self) -> &crate::Reg<fcclkselx0::FCCLKSELX0_SPEC> {
340 unsafe {
341 &*(((self as *const Self) as *const u8).add(688usize)
342 as *const crate::Reg<fcclkselx0::FCCLKSELX0_SPEC>)
343 }
344 }
345 #[doc = "0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider"]
346 #[inline(always)]
347 pub fn fcclksel0(&self) -> &crate::Reg<fcclksel0::FCCLKSEL0_SPEC> {
348 unsafe {
349 &*(((self as *const Self) as *const u8).add(688usize)
350 as *const crate::Reg<fcclksel0::FCCLKSEL0_SPEC>)
351 }
352 }
353 #[doc = "0x2b4 - Peripheral reset control register"]
354 #[inline(always)]
355 pub fn fcclkselx1(&self) -> &crate::Reg<fcclkselx1::FCCLKSELX1_SPEC> {
356 unsafe {
357 &*(((self as *const Self) as *const u8).add(692usize)
358 as *const crate::Reg<fcclkselx1::FCCLKSELX1_SPEC>)
359 }
360 }
361 #[doc = "0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider"]
362 #[inline(always)]
363 pub fn fcclksel1(&self) -> &crate::Reg<fcclksel1::FCCLKSEL1_SPEC> {
364 unsafe {
365 &*(((self as *const Self) as *const u8).add(692usize)
366 as *const crate::Reg<fcclksel1::FCCLKSEL1_SPEC>)
367 }
368 }
369 #[doc = "0x2b8 - Peripheral reset control register"]
370 #[inline(always)]
371 pub fn fcclkselx2(&self) -> &crate::Reg<fcclkselx2::FCCLKSELX2_SPEC> {
372 unsafe {
373 &*(((self as *const Self) as *const u8).add(696usize)
374 as *const crate::Reg<fcclkselx2::FCCLKSELX2_SPEC>)
375 }
376 }
377 #[doc = "0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider"]
378 #[inline(always)]
379 pub fn fcclksel2(&self) -> &crate::Reg<fcclksel2::FCCLKSEL2_SPEC> {
380 unsafe {
381 &*(((self as *const Self) as *const u8).add(696usize)
382 as *const crate::Reg<fcclksel2::FCCLKSEL2_SPEC>)
383 }
384 }
385 #[doc = "0x2bc - Peripheral reset control register"]
386 #[inline(always)]
387 pub fn fcclkselx3(&self) -> &crate::Reg<fcclkselx3::FCCLKSELX3_SPEC> {
388 unsafe {
389 &*(((self as *const Self) as *const u8).add(700usize)
390 as *const crate::Reg<fcclkselx3::FCCLKSELX3_SPEC>)
391 }
392 }
393 #[doc = "0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider"]
394 #[inline(always)]
395 pub fn fcclksel3(&self) -> &crate::Reg<fcclksel3::FCCLKSEL3_SPEC> {
396 unsafe {
397 &*(((self as *const Self) as *const u8).add(700usize)
398 as *const crate::Reg<fcclksel3::FCCLKSEL3_SPEC>)
399 }
400 }
401 #[doc = "0x2c0 - Peripheral reset control register"]
402 #[inline(always)]
403 pub fn fcclkselx4(&self) -> &crate::Reg<fcclkselx4::FCCLKSELX4_SPEC> {
404 unsafe {
405 &*(((self as *const Self) as *const u8).add(704usize)
406 as *const crate::Reg<fcclkselx4::FCCLKSELX4_SPEC>)
407 }
408 }
409 #[doc = "0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider"]
410 #[inline(always)]
411 pub fn fcclksel4(&self) -> &crate::Reg<fcclksel4::FCCLKSEL4_SPEC> {
412 unsafe {
413 &*(((self as *const Self) as *const u8).add(704usize)
414 as *const crate::Reg<fcclksel4::FCCLKSEL4_SPEC>)
415 }
416 }
417 #[doc = "0x2c4 - Peripheral reset control register"]
418 #[inline(always)]
419 pub fn fcclkselx5(&self) -> &crate::Reg<fcclkselx5::FCCLKSELX5_SPEC> {
420 unsafe {
421 &*(((self as *const Self) as *const u8).add(708usize)
422 as *const crate::Reg<fcclkselx5::FCCLKSELX5_SPEC>)
423 }
424 }
425 #[doc = "0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider"]
426 #[inline(always)]
427 pub fn fcclksel5(&self) -> &crate::Reg<fcclksel5::FCCLKSEL5_SPEC> {
428 unsafe {
429 &*(((self as *const Self) as *const u8).add(708usize)
430 as *const crate::Reg<fcclksel5::FCCLKSEL5_SPEC>)
431 }
432 }
433 #[doc = "0x2c8 - Peripheral reset control register"]
434 #[inline(always)]
435 pub fn fcclkselx6(&self) -> &crate::Reg<fcclkselx6::FCCLKSELX6_SPEC> {
436 unsafe {
437 &*(((self as *const Self) as *const u8).add(712usize)
438 as *const crate::Reg<fcclkselx6::FCCLKSELX6_SPEC>)
439 }
440 }
441 #[doc = "0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider"]
442 #[inline(always)]
443 pub fn fcclksel6(&self) -> &crate::Reg<fcclksel6::FCCLKSEL6_SPEC> {
444 unsafe {
445 &*(((self as *const Self) as *const u8).add(712usize)
446 as *const crate::Reg<fcclksel6::FCCLKSEL6_SPEC>)
447 }
448 }
449 #[doc = "0x2cc - Peripheral reset control register"]
450 #[inline(always)]
451 pub fn fcclkselx7(&self) -> &crate::Reg<fcclkselx7::FCCLKSELX7_SPEC> {
452 unsafe {
453 &*(((self as *const Self) as *const u8).add(716usize)
454 as *const crate::Reg<fcclkselx7::FCCLKSELX7_SPEC>)
455 }
456 }
457 #[doc = "0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider"]
458 #[inline(always)]
459 pub fn fcclksel7(&self) -> &crate::Reg<fcclksel7::FCCLKSEL7_SPEC> {
460 unsafe {
461 &*(((self as *const Self) as *const u8).add(716usize)
462 as *const crate::Reg<fcclksel7::FCCLKSEL7_SPEC>)
463 }
464 }
465 #[doc = "0x320 - Peripheral reset control register"]
466 #[inline(always)]
467 pub fn flexfrgxctrl0(&self) -> &crate::Reg<flexfrgxctrl0::FLEXFRGXCTRL0_SPEC> {
468 unsafe {
469 &*(((self as *const Self) as *const u8).add(800usize)
470 as *const crate::Reg<flexfrgxctrl0::FLEXFRGXCTRL0_SPEC>)
471 }
472 }
473 #[doc = "0x320 - Fractional rate divider for flexcomm 0"]
474 #[inline(always)]
475 pub fn flexfrg0ctrl(&self) -> &crate::Reg<flexfrg0ctrl::FLEXFRG0CTRL_SPEC> {
476 unsafe {
477 &*(((self as *const Self) as *const u8).add(800usize)
478 as *const crate::Reg<flexfrg0ctrl::FLEXFRG0CTRL_SPEC>)
479 }
480 }
481 #[doc = "0x324 - Peripheral reset control register"]
482 #[inline(always)]
483 pub fn flexfrgxctrl1(&self) -> &crate::Reg<flexfrgxctrl1::FLEXFRGXCTRL1_SPEC> {
484 unsafe {
485 &*(((self as *const Self) as *const u8).add(804usize)
486 as *const crate::Reg<flexfrgxctrl1::FLEXFRGXCTRL1_SPEC>)
487 }
488 }
489 #[doc = "0x324 - Fractional rate divider for flexcomm 1"]
490 #[inline(always)]
491 pub fn flexfrg1ctrl(&self) -> &crate::Reg<flexfrg1ctrl::FLEXFRG1CTRL_SPEC> {
492 unsafe {
493 &*(((self as *const Self) as *const u8).add(804usize)
494 as *const crate::Reg<flexfrg1ctrl::FLEXFRG1CTRL_SPEC>)
495 }
496 }
497 #[doc = "0x328 - Peripheral reset control register"]
498 #[inline(always)]
499 pub fn flexfrgxctrl2(&self) -> &crate::Reg<flexfrgxctrl2::FLEXFRGXCTRL2_SPEC> {
500 unsafe {
501 &*(((self as *const Self) as *const u8).add(808usize)
502 as *const crate::Reg<flexfrgxctrl2::FLEXFRGXCTRL2_SPEC>)
503 }
504 }
505 #[doc = "0x328 - Fractional rate divider for flexcomm 2"]
506 #[inline(always)]
507 pub fn flexfrg2ctrl(&self) -> &crate::Reg<flexfrg2ctrl::FLEXFRG2CTRL_SPEC> {
508 unsafe {
509 &*(((self as *const Self) as *const u8).add(808usize)
510 as *const crate::Reg<flexfrg2ctrl::FLEXFRG2CTRL_SPEC>)
511 }
512 }
513 #[doc = "0x32c - Peripheral reset control register"]
514 #[inline(always)]
515 pub fn flexfrgxctrl3(&self) -> &crate::Reg<flexfrgxctrl3::FLEXFRGXCTRL3_SPEC> {
516 unsafe {
517 &*(((self as *const Self) as *const u8).add(812usize)
518 as *const crate::Reg<flexfrgxctrl3::FLEXFRGXCTRL3_SPEC>)
519 }
520 }
521 #[doc = "0x32c - Fractional rate divider for flexcomm 3"]
522 #[inline(always)]
523 pub fn flexfrg3ctrl(&self) -> &crate::Reg<flexfrg3ctrl::FLEXFRG3CTRL_SPEC> {
524 unsafe {
525 &*(((self as *const Self) as *const u8).add(812usize)
526 as *const crate::Reg<flexfrg3ctrl::FLEXFRG3CTRL_SPEC>)
527 }
528 }
529 #[doc = "0x330 - Peripheral reset control register"]
530 #[inline(always)]
531 pub fn flexfrgxctrl4(&self) -> &crate::Reg<flexfrgxctrl4::FLEXFRGXCTRL4_SPEC> {
532 unsafe {
533 &*(((self as *const Self) as *const u8).add(816usize)
534 as *const crate::Reg<flexfrgxctrl4::FLEXFRGXCTRL4_SPEC>)
535 }
536 }
537 #[doc = "0x330 - Fractional rate divider for flexcomm 4"]
538 #[inline(always)]
539 pub fn flexfrg4ctrl(&self) -> &crate::Reg<flexfrg4ctrl::FLEXFRG4CTRL_SPEC> {
540 unsafe {
541 &*(((self as *const Self) as *const u8).add(816usize)
542 as *const crate::Reg<flexfrg4ctrl::FLEXFRG4CTRL_SPEC>)
543 }
544 }
545 #[doc = "0x334 - Peripheral reset control register"]
546 #[inline(always)]
547 pub fn flexfrgxctrl5(&self) -> &crate::Reg<flexfrgxctrl5::FLEXFRGXCTRL5_SPEC> {
548 unsafe {
549 &*(((self as *const Self) as *const u8).add(820usize)
550 as *const crate::Reg<flexfrgxctrl5::FLEXFRGXCTRL5_SPEC>)
551 }
552 }
553 #[doc = "0x334 - Fractional rate divider for flexcomm 5"]
554 #[inline(always)]
555 pub fn flexfrg5ctrl(&self) -> &crate::Reg<flexfrg5ctrl::FLEXFRG5CTRL_SPEC> {
556 unsafe {
557 &*(((self as *const Self) as *const u8).add(820usize)
558 as *const crate::Reg<flexfrg5ctrl::FLEXFRG5CTRL_SPEC>)
559 }
560 }
561 #[doc = "0x338 - Peripheral reset control register"]
562 #[inline(always)]
563 pub fn flexfrgxctrl6(&self) -> &crate::Reg<flexfrgxctrl6::FLEXFRGXCTRL6_SPEC> {
564 unsafe {
565 &*(((self as *const Self) as *const u8).add(824usize)
566 as *const crate::Reg<flexfrgxctrl6::FLEXFRGXCTRL6_SPEC>)
567 }
568 }
569 #[doc = "0x338 - Fractional rate divider for flexcomm 6"]
570 #[inline(always)]
571 pub fn flexfrg6ctrl(&self) -> &crate::Reg<flexfrg6ctrl::FLEXFRG6CTRL_SPEC> {
572 unsafe {
573 &*(((self as *const Self) as *const u8).add(824usize)
574 as *const crate::Reg<flexfrg6ctrl::FLEXFRG6CTRL_SPEC>)
575 }
576 }
577 #[doc = "0x33c - Peripheral reset control register"]
578 #[inline(always)]
579 pub fn flexfrgxctrl7(&self) -> &crate::Reg<flexfrgxctrl7::FLEXFRGXCTRL7_SPEC> {
580 unsafe {
581 &*(((self as *const Self) as *const u8).add(828usize)
582 as *const crate::Reg<flexfrgxctrl7::FLEXFRGXCTRL7_SPEC>)
583 }
584 }
585 #[doc = "0x33c - Fractional rate divider for flexcomm 7"]
586 #[inline(always)]
587 pub fn flexfrg7ctrl(&self) -> &crate::Reg<flexfrg7ctrl::FLEXFRG7CTRL_SPEC> {
588 unsafe {
589 &*(((self as *const Self) as *const u8).add(828usize)
590 as *const crate::Reg<flexfrg7ctrl::FLEXFRG7CTRL_SPEC>)
591 }
592 }
593}
594#[doc = "MEMORYREMAP register accessor: an alias for `Reg<MEMORYREMAP_SPEC>`"]
595pub type MEMORYREMAP = crate::Reg<memoryremap::MEMORYREMAP_SPEC>;
596#[doc = "Memory Remap control register"]
597pub mod memoryremap;
598#[doc = "AHBMATPRIO register accessor: an alias for `Reg<AHBMATPRIO_SPEC>`"]
599pub type AHBMATPRIO = crate::Reg<ahbmatprio::AHBMATPRIO_SPEC>;
600#[doc = "AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest"]
601pub mod ahbmatprio;
602#[doc = "CPU0STCKCAL register accessor: an alias for `Reg<CPU0STCKCAL_SPEC>`"]
603pub type CPU0STCKCAL = crate::Reg<cpu0stckcal::CPU0STCKCAL_SPEC>;
604#[doc = "System tick calibration for secure part of CPU0"]
605pub mod cpu0stckcal;
606#[doc = "CPU0NSTCKCAL register accessor: an alias for `Reg<CPU0NSTCKCAL_SPEC>`"]
607pub type CPU0NSTCKCAL = crate::Reg<cpu0nstckcal::CPU0NSTCKCAL_SPEC>;
608#[doc = "System tick calibration for non-secure part of CPU0"]
609pub mod cpu0nstckcal;
610#[doc = "CPU1STCKCAL register accessor: an alias for `Reg<CPU1STCKCAL_SPEC>`"]
611pub type CPU1STCKCAL = crate::Reg<cpu1stckcal::CPU1STCKCAL_SPEC>;
612#[doc = "System tick calibration for CPU1"]
613pub mod cpu1stckcal;
614#[doc = "NMISRC register accessor: an alias for `Reg<NMISRC_SPEC>`"]
615pub type NMISRC = crate::Reg<nmisrc::NMISRC_SPEC>;
616#[doc = "NMI Source Select"]
617pub mod nmisrc;
618#[doc = "PRESETCTRL0 register accessor: an alias for `Reg<PRESETCTRL0_SPEC>`"]
619pub type PRESETCTRL0 = crate::Reg<presetctrl0::PRESETCTRL0_SPEC>;
620#[doc = "Peripheral reset control 0"]
621pub mod presetctrl0;
622#[doc = "PRESETCTRL1 register accessor: an alias for `Reg<PRESETCTRL1_SPEC>`"]
623pub type PRESETCTRL1 = crate::Reg<presetctrl1::PRESETCTRL1_SPEC>;
624#[doc = "Peripheral reset control 1"]
625pub mod presetctrl1;
626#[doc = "PRESETCTRL2 register accessor: an alias for `Reg<PRESETCTRL2_SPEC>`"]
627pub type PRESETCTRL2 = crate::Reg<presetctrl2::PRESETCTRL2_SPEC>;
628#[doc = "Peripheral reset control 2"]
629pub mod presetctrl2;
630#[doc = "PRESETCTRLSET register accessor: an alias for `Reg<PRESETCTRLSET_SPEC>`"]
631pub type PRESETCTRLSET = crate::Reg<presetctrlset::PRESETCTRLSET_SPEC>;
632#[doc = "Peripheral reset control set register"]
633pub mod presetctrlset;
634#[doc = "PRESETCTRLCLR register accessor: an alias for `Reg<PRESETCTRLCLR_SPEC>`"]
635pub type PRESETCTRLCLR = crate::Reg<presetctrlclr::PRESETCTRLCLR_SPEC>;
636#[doc = "Peripheral reset control clear register"]
637pub mod presetctrlclr;
638#[doc = "SWR_RESET register accessor: an alias for `Reg<SWR_RESET_SPEC>`"]
639pub type SWR_RESET = crate::Reg<swr_reset::SWR_RESET_SPEC>;
640#[doc = "generate a software_reset"]
641pub mod swr_reset;
642#[doc = "AHBCLKCTRL0 register accessor: an alias for `Reg<AHBCLKCTRL0_SPEC>`"]
643pub type AHBCLKCTRL0 = crate::Reg<ahbclkctrl0::AHBCLKCTRL0_SPEC>;
644#[doc = "AHB Clock control 0"]
645pub mod ahbclkctrl0;
646#[doc = "AHBCLKCTRL1 register accessor: an alias for `Reg<AHBCLKCTRL1_SPEC>`"]
647pub type AHBCLKCTRL1 = crate::Reg<ahbclkctrl1::AHBCLKCTRL1_SPEC>;
648#[doc = "AHB Clock control 1"]
649pub mod ahbclkctrl1;
650#[doc = "AHBCLKCTRL2 register accessor: an alias for `Reg<AHBCLKCTRL2_SPEC>`"]
651pub type AHBCLKCTRL2 = crate::Reg<ahbclkctrl2::AHBCLKCTRL2_SPEC>;
652#[doc = "AHB Clock control 2"]
653pub mod ahbclkctrl2;
654#[doc = "AHBCLKCTRLSET register accessor: an alias for `Reg<AHBCLKCTRLSET_SPEC>`"]
655pub type AHBCLKCTRLSET = crate::Reg<ahbclkctrlset::AHBCLKCTRLSET_SPEC>;
656#[doc = "Peripheral reset control register"]
657pub mod ahbclkctrlset;
658#[doc = "AHBCLKCTRLCLR register accessor: an alias for `Reg<AHBCLKCTRLCLR_SPEC>`"]
659pub type AHBCLKCTRLCLR = crate::Reg<ahbclkctrlclr::AHBCLKCTRLCLR_SPEC>;
660#[doc = "Peripheral reset control register"]
661pub mod ahbclkctrlclr;
662#[doc = "SYSTICKCLKSEL0 register accessor: an alias for `Reg<SYSTICKCLKSEL0_SPEC>`"]
663pub type SYSTICKCLKSEL0 = crate::Reg<systickclksel0::SYSTICKCLKSEL0_SPEC>;
664#[doc = "System Tick Timer for CPU0 source select"]
665pub mod systickclksel0;
666#[doc = "SYSTICKCLKSELX0 register accessor: an alias for `Reg<SYSTICKCLKSELX0_SPEC>`"]
667pub type SYSTICKCLKSELX0 = crate::Reg<systickclkselx0::SYSTICKCLKSELX0_SPEC>;
668#[doc = "Peripheral reset control register"]
669pub mod systickclkselx0;
670#[doc = "SYSTICKCLKSEL1 register accessor: an alias for `Reg<SYSTICKCLKSEL1_SPEC>`"]
671pub type SYSTICKCLKSEL1 = crate::Reg<systickclksel1::SYSTICKCLKSEL1_SPEC>;
672#[doc = "System Tick Timer for CPU1 source select"]
673pub mod systickclksel1;
674#[doc = "SYSTICKCLKSELX1 register accessor: an alias for `Reg<SYSTICKCLKSELX1_SPEC>`"]
675pub type SYSTICKCLKSELX1 = crate::Reg<systickclkselx1::SYSTICKCLKSELX1_SPEC>;
676#[doc = "Peripheral reset control register"]
677pub mod systickclkselx1;
678#[doc = "TRACECLKSEL register accessor: an alias for `Reg<TRACECLKSEL_SPEC>`"]
679pub type TRACECLKSEL = crate::Reg<traceclksel::TRACECLKSEL_SPEC>;
680#[doc = "Trace clock source select"]
681pub mod traceclksel;
682#[doc = "CTIMERCLKSEL0 register accessor: an alias for `Reg<CTIMERCLKSEL0_SPEC>`"]
683pub type CTIMERCLKSEL0 = crate::Reg<ctimerclksel0::CTIMERCLKSEL0_SPEC>;
684#[doc = "CTimer 0 clock source select"]
685pub mod ctimerclksel0;
686#[doc = "CTIMERCLKSELX0 register accessor: an alias for `Reg<CTIMERCLKSELX0_SPEC>`"]
687pub type CTIMERCLKSELX0 = crate::Reg<ctimerclkselx0::CTIMERCLKSELX0_SPEC>;
688#[doc = "Peripheral reset control register"]
689pub mod ctimerclkselx0;
690#[doc = "CTIMERCLKSEL1 register accessor: an alias for `Reg<CTIMERCLKSEL1_SPEC>`"]
691pub type CTIMERCLKSEL1 = crate::Reg<ctimerclksel1::CTIMERCLKSEL1_SPEC>;
692#[doc = "CTimer 1 clock source select"]
693pub mod ctimerclksel1;
694#[doc = "CTIMERCLKSELX1 register accessor: an alias for `Reg<CTIMERCLKSELX1_SPEC>`"]
695pub type CTIMERCLKSELX1 = crate::Reg<ctimerclkselx1::CTIMERCLKSELX1_SPEC>;
696#[doc = "Peripheral reset control register"]
697pub mod ctimerclkselx1;
698#[doc = "CTIMERCLKSEL2 register accessor: an alias for `Reg<CTIMERCLKSEL2_SPEC>`"]
699pub type CTIMERCLKSEL2 = crate::Reg<ctimerclksel2::CTIMERCLKSEL2_SPEC>;
700#[doc = "CTimer 2 clock source select"]
701pub mod ctimerclksel2;
702#[doc = "CTIMERCLKSELX2 register accessor: an alias for `Reg<CTIMERCLKSELX2_SPEC>`"]
703pub type CTIMERCLKSELX2 = crate::Reg<ctimerclkselx2::CTIMERCLKSELX2_SPEC>;
704#[doc = "Peripheral reset control register"]
705pub mod ctimerclkselx2;
706#[doc = "CTIMERCLKSEL3 register accessor: an alias for `Reg<CTIMERCLKSEL3_SPEC>`"]
707pub type CTIMERCLKSEL3 = crate::Reg<ctimerclksel3::CTIMERCLKSEL3_SPEC>;
708#[doc = "CTimer 3 clock source select"]
709pub mod ctimerclksel3;
710#[doc = "CTIMERCLKSELX3 register accessor: an alias for `Reg<CTIMERCLKSELX3_SPEC>`"]
711pub type CTIMERCLKSELX3 = crate::Reg<ctimerclkselx3::CTIMERCLKSELX3_SPEC>;
712#[doc = "Peripheral reset control register"]
713pub mod ctimerclkselx3;
714#[doc = "CTIMERCLKSEL4 register accessor: an alias for `Reg<CTIMERCLKSEL4_SPEC>`"]
715pub type CTIMERCLKSEL4 = crate::Reg<ctimerclksel4::CTIMERCLKSEL4_SPEC>;
716#[doc = "CTimer 4 clock source select"]
717pub mod ctimerclksel4;
718#[doc = "CTIMERCLKSELX4 register accessor: an alias for `Reg<CTIMERCLKSELX4_SPEC>`"]
719pub type CTIMERCLKSELX4 = crate::Reg<ctimerclkselx4::CTIMERCLKSELX4_SPEC>;
720#[doc = "Peripheral reset control register"]
721pub mod ctimerclkselx4;
722#[doc = "MAINCLKSELA register accessor: an alias for `Reg<MAINCLKSELA_SPEC>`"]
723pub type MAINCLKSELA = crate::Reg<mainclksela::MAINCLKSELA_SPEC>;
724#[doc = "Main clock A source select"]
725pub mod mainclksela;
726#[doc = "MAINCLKSELB register accessor: an alias for `Reg<MAINCLKSELB_SPEC>`"]
727pub type MAINCLKSELB = crate::Reg<mainclkselb::MAINCLKSELB_SPEC>;
728#[doc = "Main clock source select"]
729pub mod mainclkselb;
730#[doc = "CLKOUTSEL register accessor: an alias for `Reg<CLKOUTSEL_SPEC>`"]
731pub type CLKOUTSEL = crate::Reg<clkoutsel::CLKOUTSEL_SPEC>;
732#[doc = "CLKOUT clock source select"]
733pub mod clkoutsel;
734#[doc = "PLL0CLKSEL register accessor: an alias for `Reg<PLL0CLKSEL_SPEC>`"]
735pub type PLL0CLKSEL = crate::Reg<pll0clksel::PLL0CLKSEL_SPEC>;
736#[doc = "PLL0 clock source select"]
737pub mod pll0clksel;
738#[doc = "PLL1CLKSEL register accessor: an alias for `Reg<PLL1CLKSEL_SPEC>`"]
739pub type PLL1CLKSEL = crate::Reg<pll1clksel::PLL1CLKSEL_SPEC>;
740#[doc = "PLL1 clock source select"]
741pub mod pll1clksel;
742#[doc = "ADCCLKSEL register accessor: an alias for `Reg<ADCCLKSEL_SPEC>`"]
743pub type ADCCLKSEL = crate::Reg<adcclksel::ADCCLKSEL_SPEC>;
744#[doc = "ADC clock source select"]
745pub mod adcclksel;
746#[doc = "USB0CLKSEL register accessor: an alias for `Reg<USB0CLKSEL_SPEC>`"]
747pub type USB0CLKSEL = crate::Reg<usb0clksel::USB0CLKSEL_SPEC>;
748#[doc = "FS USB clock source select"]
749pub mod usb0clksel;
750#[doc = "FCCLKSEL0 register accessor: an alias for `Reg<FCCLKSEL0_SPEC>`"]
751pub type FCCLKSEL0 = crate::Reg<fcclksel0::FCCLKSEL0_SPEC>;
752#[doc = "Flexcomm Interface 0 clock source select for Fractional Rate Divider"]
753pub mod fcclksel0;
754#[doc = "FCCLKSELX0 register accessor: an alias for `Reg<FCCLKSELX0_SPEC>`"]
755pub type FCCLKSELX0 = crate::Reg<fcclkselx0::FCCLKSELX0_SPEC>;
756#[doc = "Peripheral reset control register"]
757pub mod fcclkselx0;
758#[doc = "FCCLKSEL1 register accessor: an alias for `Reg<FCCLKSEL1_SPEC>`"]
759pub type FCCLKSEL1 = crate::Reg<fcclksel1::FCCLKSEL1_SPEC>;
760#[doc = "Flexcomm Interface 1 clock source select for Fractional Rate Divider"]
761pub mod fcclksel1;
762#[doc = "FCCLKSELX1 register accessor: an alias for `Reg<FCCLKSELX1_SPEC>`"]
763pub type FCCLKSELX1 = crate::Reg<fcclkselx1::FCCLKSELX1_SPEC>;
764#[doc = "Peripheral reset control register"]
765pub mod fcclkselx1;
766#[doc = "FCCLKSEL2 register accessor: an alias for `Reg<FCCLKSEL2_SPEC>`"]
767pub type FCCLKSEL2 = crate::Reg<fcclksel2::FCCLKSEL2_SPEC>;
768#[doc = "Flexcomm Interface 2 clock source select for Fractional Rate Divider"]
769pub mod fcclksel2;
770#[doc = "FCCLKSELX2 register accessor: an alias for `Reg<FCCLKSELX2_SPEC>`"]
771pub type FCCLKSELX2 = crate::Reg<fcclkselx2::FCCLKSELX2_SPEC>;
772#[doc = "Peripheral reset control register"]
773pub mod fcclkselx2;
774#[doc = "FCCLKSEL3 register accessor: an alias for `Reg<FCCLKSEL3_SPEC>`"]
775pub type FCCLKSEL3 = crate::Reg<fcclksel3::FCCLKSEL3_SPEC>;
776#[doc = "Flexcomm Interface 3 clock source select for Fractional Rate Divider"]
777pub mod fcclksel3;
778#[doc = "FCCLKSELX3 register accessor: an alias for `Reg<FCCLKSELX3_SPEC>`"]
779pub type FCCLKSELX3 = crate::Reg<fcclkselx3::FCCLKSELX3_SPEC>;
780#[doc = "Peripheral reset control register"]
781pub mod fcclkselx3;
782#[doc = "FCCLKSEL4 register accessor: an alias for `Reg<FCCLKSEL4_SPEC>`"]
783pub type FCCLKSEL4 = crate::Reg<fcclksel4::FCCLKSEL4_SPEC>;
784#[doc = "Flexcomm Interface 4 clock source select for Fractional Rate Divider"]
785pub mod fcclksel4;
786#[doc = "FCCLKSELX4 register accessor: an alias for `Reg<FCCLKSELX4_SPEC>`"]
787pub type FCCLKSELX4 = crate::Reg<fcclkselx4::FCCLKSELX4_SPEC>;
788#[doc = "Peripheral reset control register"]
789pub mod fcclkselx4;
790#[doc = "FCCLKSEL5 register accessor: an alias for `Reg<FCCLKSEL5_SPEC>`"]
791pub type FCCLKSEL5 = crate::Reg<fcclksel5::FCCLKSEL5_SPEC>;
792#[doc = "Flexcomm Interface 5 clock source select for Fractional Rate Divider"]
793pub mod fcclksel5;
794#[doc = "FCCLKSELX5 register accessor: an alias for `Reg<FCCLKSELX5_SPEC>`"]
795pub type FCCLKSELX5 = crate::Reg<fcclkselx5::FCCLKSELX5_SPEC>;
796#[doc = "Peripheral reset control register"]
797pub mod fcclkselx5;
798#[doc = "FCCLKSEL6 register accessor: an alias for `Reg<FCCLKSEL6_SPEC>`"]
799pub type FCCLKSEL6 = crate::Reg<fcclksel6::FCCLKSEL6_SPEC>;
800#[doc = "Flexcomm Interface 6 clock source select for Fractional Rate Divider"]
801pub mod fcclksel6;
802#[doc = "FCCLKSELX6 register accessor: an alias for `Reg<FCCLKSELX6_SPEC>`"]
803pub type FCCLKSELX6 = crate::Reg<fcclkselx6::FCCLKSELX6_SPEC>;
804#[doc = "Peripheral reset control register"]
805pub mod fcclkselx6;
806#[doc = "FCCLKSEL7 register accessor: an alias for `Reg<FCCLKSEL7_SPEC>`"]
807pub type FCCLKSEL7 = crate::Reg<fcclksel7::FCCLKSEL7_SPEC>;
808#[doc = "Flexcomm Interface 7 clock source select for Fractional Rate Divider"]
809pub mod fcclksel7;
810#[doc = "FCCLKSELX7 register accessor: an alias for `Reg<FCCLKSELX7_SPEC>`"]
811pub type FCCLKSELX7 = crate::Reg<fcclkselx7::FCCLKSELX7_SPEC>;
812#[doc = "Peripheral reset control register"]
813pub mod fcclkselx7;
814#[doc = "HSLSPICLKSEL register accessor: an alias for `Reg<HSLSPICLKSEL_SPEC>`"]
815pub type HSLSPICLKSEL = crate::Reg<hslspiclksel::HSLSPICLKSEL_SPEC>;
816#[doc = "HS LSPI clock source select"]
817pub mod hslspiclksel;
818#[doc = "MCLKCLKSEL register accessor: an alias for `Reg<MCLKCLKSEL_SPEC>`"]
819pub type MCLKCLKSEL = crate::Reg<mclkclksel::MCLKCLKSEL_SPEC>;
820#[doc = "MCLK clock source select"]
821pub mod mclkclksel;
822#[doc = "SCTCLKSEL register accessor: an alias for `Reg<SCTCLKSEL_SPEC>`"]
823pub type SCTCLKSEL = crate::Reg<sctclksel::SCTCLKSEL_SPEC>;
824#[doc = "SCTimer/PWM clock source select"]
825pub mod sctclksel;
826#[doc = "SDIOCLKSEL register accessor: an alias for `Reg<SDIOCLKSEL_SPEC>`"]
827pub type SDIOCLKSEL = crate::Reg<sdioclksel::SDIOCLKSEL_SPEC>;
828#[doc = "SDIO clock source select"]
829pub mod sdioclksel;
830#[doc = "SYSTICKCLKDIV0 register accessor: an alias for `Reg<SYSTICKCLKDIV0_SPEC>`"]
831pub type SYSTICKCLKDIV0 = crate::Reg<systickclkdiv0::SYSTICKCLKDIV0_SPEC>;
832#[doc = "System Tick Timer divider for CPU0"]
833pub mod systickclkdiv0;
834#[doc = "SYSTICKCLKDIV1 register accessor: an alias for `Reg<SYSTICKCLKDIV1_SPEC>`"]
835pub type SYSTICKCLKDIV1 = crate::Reg<systickclkdiv1::SYSTICKCLKDIV1_SPEC>;
836#[doc = "System Tick Timer divider for CPU1"]
837pub mod systickclkdiv1;
838#[doc = "TRACECLKDIV register accessor: an alias for `Reg<TRACECLKDIV_SPEC>`"]
839pub type TRACECLKDIV = crate::Reg<traceclkdiv::TRACECLKDIV_SPEC>;
840#[doc = "TRACE clock divider"]
841pub mod traceclkdiv;
842#[doc = "FLEXFRG0CTRL register accessor: an alias for `Reg<FLEXFRG0CTRL_SPEC>`"]
843pub type FLEXFRG0CTRL = crate::Reg<flexfrg0ctrl::FLEXFRG0CTRL_SPEC>;
844#[doc = "Fractional rate divider for flexcomm 0"]
845pub mod flexfrg0ctrl;
846#[doc = "FLEXFRGXCTRL0 register accessor: an alias for `Reg<FLEXFRGXCTRL0_SPEC>`"]
847pub type FLEXFRGXCTRL0 = crate::Reg<flexfrgxctrl0::FLEXFRGXCTRL0_SPEC>;
848#[doc = "Peripheral reset control register"]
849pub mod flexfrgxctrl0;
850#[doc = "FLEXFRG1CTRL register accessor: an alias for `Reg<FLEXFRG1CTRL_SPEC>`"]
851pub type FLEXFRG1CTRL = crate::Reg<flexfrg1ctrl::FLEXFRG1CTRL_SPEC>;
852#[doc = "Fractional rate divider for flexcomm 1"]
853pub mod flexfrg1ctrl;
854#[doc = "FLEXFRGXCTRL1 register accessor: an alias for `Reg<FLEXFRGXCTRL1_SPEC>`"]
855pub type FLEXFRGXCTRL1 = crate::Reg<flexfrgxctrl1::FLEXFRGXCTRL1_SPEC>;
856#[doc = "Peripheral reset control register"]
857pub mod flexfrgxctrl1;
858#[doc = "FLEXFRG2CTRL register accessor: an alias for `Reg<FLEXFRG2CTRL_SPEC>`"]
859pub type FLEXFRG2CTRL = crate::Reg<flexfrg2ctrl::FLEXFRG2CTRL_SPEC>;
860#[doc = "Fractional rate divider for flexcomm 2"]
861pub mod flexfrg2ctrl;
862#[doc = "FLEXFRGXCTRL2 register accessor: an alias for `Reg<FLEXFRGXCTRL2_SPEC>`"]
863pub type FLEXFRGXCTRL2 = crate::Reg<flexfrgxctrl2::FLEXFRGXCTRL2_SPEC>;
864#[doc = "Peripheral reset control register"]
865pub mod flexfrgxctrl2;
866#[doc = "FLEXFRG3CTRL register accessor: an alias for `Reg<FLEXFRG3CTRL_SPEC>`"]
867pub type FLEXFRG3CTRL = crate::Reg<flexfrg3ctrl::FLEXFRG3CTRL_SPEC>;
868#[doc = "Fractional rate divider for flexcomm 3"]
869pub mod flexfrg3ctrl;
870#[doc = "FLEXFRGXCTRL3 register accessor: an alias for `Reg<FLEXFRGXCTRL3_SPEC>`"]
871pub type FLEXFRGXCTRL3 = crate::Reg<flexfrgxctrl3::FLEXFRGXCTRL3_SPEC>;
872#[doc = "Peripheral reset control register"]
873pub mod flexfrgxctrl3;
874#[doc = "FLEXFRG4CTRL register accessor: an alias for `Reg<FLEXFRG4CTRL_SPEC>`"]
875pub type FLEXFRG4CTRL = crate::Reg<flexfrg4ctrl::FLEXFRG4CTRL_SPEC>;
876#[doc = "Fractional rate divider for flexcomm 4"]
877pub mod flexfrg4ctrl;
878#[doc = "FLEXFRGXCTRL4 register accessor: an alias for `Reg<FLEXFRGXCTRL4_SPEC>`"]
879pub type FLEXFRGXCTRL4 = crate::Reg<flexfrgxctrl4::FLEXFRGXCTRL4_SPEC>;
880#[doc = "Peripheral reset control register"]
881pub mod flexfrgxctrl4;
882#[doc = "FLEXFRG5CTRL register accessor: an alias for `Reg<FLEXFRG5CTRL_SPEC>`"]
883pub type FLEXFRG5CTRL = crate::Reg<flexfrg5ctrl::FLEXFRG5CTRL_SPEC>;
884#[doc = "Fractional rate divider for flexcomm 5"]
885pub mod flexfrg5ctrl;
886#[doc = "FLEXFRGXCTRL5 register accessor: an alias for `Reg<FLEXFRGXCTRL5_SPEC>`"]
887pub type FLEXFRGXCTRL5 = crate::Reg<flexfrgxctrl5::FLEXFRGXCTRL5_SPEC>;
888#[doc = "Peripheral reset control register"]
889pub mod flexfrgxctrl5;
890#[doc = "FLEXFRG6CTRL register accessor: an alias for `Reg<FLEXFRG6CTRL_SPEC>`"]
891pub type FLEXFRG6CTRL = crate::Reg<flexfrg6ctrl::FLEXFRG6CTRL_SPEC>;
892#[doc = "Fractional rate divider for flexcomm 6"]
893pub mod flexfrg6ctrl;
894#[doc = "FLEXFRGXCTRL6 register accessor: an alias for `Reg<FLEXFRGXCTRL6_SPEC>`"]
895pub type FLEXFRGXCTRL6 = crate::Reg<flexfrgxctrl6::FLEXFRGXCTRL6_SPEC>;
896#[doc = "Peripheral reset control register"]
897pub mod flexfrgxctrl6;
898#[doc = "FLEXFRG7CTRL register accessor: an alias for `Reg<FLEXFRG7CTRL_SPEC>`"]
899pub type FLEXFRG7CTRL = crate::Reg<flexfrg7ctrl::FLEXFRG7CTRL_SPEC>;
900#[doc = "Fractional rate divider for flexcomm 7"]
901pub mod flexfrg7ctrl;
902#[doc = "FLEXFRGXCTRL7 register accessor: an alias for `Reg<FLEXFRGXCTRL7_SPEC>`"]
903pub type FLEXFRGXCTRL7 = crate::Reg<flexfrgxctrl7::FLEXFRGXCTRL7_SPEC>;
904#[doc = "Peripheral reset control register"]
905pub mod flexfrgxctrl7;
906#[doc = "AHBCLKDIV register accessor: an alias for `Reg<AHBCLKDIV_SPEC>`"]
907pub type AHBCLKDIV = crate::Reg<ahbclkdiv::AHBCLKDIV_SPEC>;
908#[doc = "System clock divider"]
909pub mod ahbclkdiv;
910#[doc = "CLKOUTDIV register accessor: an alias for `Reg<CLKOUTDIV_SPEC>`"]
911pub type CLKOUTDIV = crate::Reg<clkoutdiv::CLKOUTDIV_SPEC>;
912#[doc = "CLKOUT clock divider"]
913pub mod clkoutdiv;
914#[doc = "FROHFDIV register accessor: an alias for `Reg<FROHFDIV_SPEC>`"]
915pub type FROHFDIV = crate::Reg<frohfdiv::FROHFDIV_SPEC>;
916#[doc = "FRO_HF (96MHz) clock divider"]
917pub mod frohfdiv;
918#[doc = "WDTCLKDIV register accessor: an alias for `Reg<WDTCLKDIV_SPEC>`"]
919pub type WDTCLKDIV = crate::Reg<wdtclkdiv::WDTCLKDIV_SPEC>;
920#[doc = "WDT clock divider"]
921pub mod wdtclkdiv;
922#[doc = "ADCCLKDIV register accessor: an alias for `Reg<ADCCLKDIV_SPEC>`"]
923pub type ADCCLKDIV = crate::Reg<adcclkdiv::ADCCLKDIV_SPEC>;
924#[doc = "ADC clock divider"]
925pub mod adcclkdiv;
926#[doc = "USB0CLKDIV register accessor: an alias for `Reg<USB0CLKDIV_SPEC>`"]
927pub type USB0CLKDIV = crate::Reg<usb0clkdiv::USB0CLKDIV_SPEC>;
928#[doc = "USB0 Clock divider"]
929pub mod usb0clkdiv;
930#[doc = "MCLKDIV register accessor: an alias for `Reg<MCLKDIV_SPEC>`"]
931pub type MCLKDIV = crate::Reg<mclkdiv::MCLKDIV_SPEC>;
932#[doc = "I2S MCLK clock divider"]
933pub mod mclkdiv;
934#[doc = "SCTCLKDIV register accessor: an alias for `Reg<SCTCLKDIV_SPEC>`"]
935pub type SCTCLKDIV = crate::Reg<sctclkdiv::SCTCLKDIV_SPEC>;
936#[doc = "SCT/PWM clock divider"]
937pub mod sctclkdiv;
938#[doc = "SDIOCLKDIV register accessor: an alias for `Reg<SDIOCLKDIV_SPEC>`"]
939pub type SDIOCLKDIV = crate::Reg<sdioclkdiv::SDIOCLKDIV_SPEC>;
940#[doc = "SDIO clock divider"]
941pub mod sdioclkdiv;
942#[doc = "PLL0CLKDIV register accessor: an alias for `Reg<PLL0CLKDIV_SPEC>`"]
943pub type PLL0CLKDIV = crate::Reg<pll0clkdiv::PLL0CLKDIV_SPEC>;
944#[doc = "PLL0 clock divider"]
945pub mod pll0clkdiv;
946#[doc = "CLOCKGENUPDATELOCKOUT register accessor: an alias for `Reg<CLOCKGENUPDATELOCKOUT_SPEC>`"]
947pub type CLOCKGENUPDATELOCKOUT = crate::Reg<clockgenupdatelockout::CLOCKGENUPDATELOCKOUT_SPEC>;
948#[doc = "Control clock configuration registers access (like xxxDIV, xxxSEL)"]
949pub mod clockgenupdatelockout;
950#[doc = "FMCCR register accessor: an alias for `Reg<FMCCR_SPEC>`"]
951pub type FMCCR = crate::Reg<fmccr::FMCCR_SPEC>;
952#[doc = "FMC configuration register"]
953pub mod fmccr;
954#[doc = "USB0NEEDCLKCTRL register accessor: an alias for `Reg<USB0NEEDCLKCTRL_SPEC>`"]
955pub type USB0NEEDCLKCTRL = crate::Reg<usb0needclkctrl::USB0NEEDCLKCTRL_SPEC>;
956#[doc = "USB0 need clock control"]
957pub mod usb0needclkctrl;
958#[doc = "USB0NEEDCLKSTAT register accessor: an alias for `Reg<USB0NEEDCLKSTAT_SPEC>`"]
959pub type USB0NEEDCLKSTAT = crate::Reg<usb0needclkstat::USB0NEEDCLKSTAT_SPEC>;
960#[doc = "USB0 need clock status"]
961pub mod usb0needclkstat;
962#[doc = "FMCFLUSH register accessor: an alias for `Reg<FMCFLUSH_SPEC>`"]
963pub type FMCFLUSH = crate::Reg<fmcflush::FMCFLUSH_SPEC>;
964#[doc = "FMCflush control"]
965pub mod fmcflush;
966#[doc = "MCLKIO register accessor: an alias for `Reg<MCLKIO_SPEC>`"]
967pub type MCLKIO = crate::Reg<mclkio::MCLKIO_SPEC>;
968#[doc = "MCLK control"]
969pub mod mclkio;
970#[doc = "USB1NEEDCLKCTRL register accessor: an alias for `Reg<USB1NEEDCLKCTRL_SPEC>`"]
971pub type USB1NEEDCLKCTRL = crate::Reg<usb1needclkctrl::USB1NEEDCLKCTRL_SPEC>;
972#[doc = "USB1 need clock control"]
973pub mod usb1needclkctrl;
974#[doc = "USB1NEEDCLKSTAT register accessor: an alias for `Reg<USB1NEEDCLKSTAT_SPEC>`"]
975pub type USB1NEEDCLKSTAT = crate::Reg<usb1needclkstat::USB1NEEDCLKSTAT_SPEC>;
976#[doc = "USB1 need clock status"]
977pub mod usb1needclkstat;
978#[doc = "SDIOCLKCTRL register accessor: an alias for `Reg<SDIOCLKCTRL_SPEC>`"]
979pub type SDIOCLKCTRL = crate::Reg<sdioclkctrl::SDIOCLKCTRL_SPEC>;
980#[doc = "SDIO CCLKIN phase and delay control"]
981pub mod sdioclkctrl;
982#[doc = "PLL1CTRL register accessor: an alias for `Reg<PLL1CTRL_SPEC>`"]
983pub type PLL1CTRL = crate::Reg<pll1ctrl::PLL1CTRL_SPEC>;
984#[doc = "PLL1 550m control"]
985pub mod pll1ctrl;
986#[doc = "PLL1STAT register accessor: an alias for `Reg<PLL1STAT_SPEC>`"]
987pub type PLL1STAT = crate::Reg<pll1stat::PLL1STAT_SPEC>;
988#[doc = "PLL1 550m status"]
989pub mod pll1stat;
990#[doc = "PLL1NDEC register accessor: an alias for `Reg<PLL1NDEC_SPEC>`"]
991pub type PLL1NDEC = crate::Reg<pll1ndec::PLL1NDEC_SPEC>;
992#[doc = "PLL1 550m N divider"]
993pub mod pll1ndec;
994#[doc = "PLL1MDEC register accessor: an alias for `Reg<PLL1MDEC_SPEC>`"]
995pub type PLL1MDEC = crate::Reg<pll1mdec::PLL1MDEC_SPEC>;
996#[doc = "PLL1 550m M divider"]
997pub mod pll1mdec;
998#[doc = "PLL1PDEC register accessor: an alias for `Reg<PLL1PDEC_SPEC>`"]
999pub type PLL1PDEC = crate::Reg<pll1pdec::PLL1PDEC_SPEC>;
1000#[doc = "PLL1 550m P divider"]
1001pub mod pll1pdec;
1002#[doc = "PLL0CTRL register accessor: an alias for `Reg<PLL0CTRL_SPEC>`"]
1003pub type PLL0CTRL = crate::Reg<pll0ctrl::PLL0CTRL_SPEC>;
1004#[doc = "PLL0 550m control"]
1005pub mod pll0ctrl;
1006#[doc = "PLL0STAT register accessor: an alias for `Reg<PLL0STAT_SPEC>`"]
1007pub type PLL0STAT = crate::Reg<pll0stat::PLL0STAT_SPEC>;
1008#[doc = "PLL0 550m status"]
1009pub mod pll0stat;
1010#[doc = "PLL0NDEC register accessor: an alias for `Reg<PLL0NDEC_SPEC>`"]
1011pub type PLL0NDEC = crate::Reg<pll0ndec::PLL0NDEC_SPEC>;
1012#[doc = "PLL0 550m N divider"]
1013pub mod pll0ndec;
1014#[doc = "PLL0PDEC register accessor: an alias for `Reg<PLL0PDEC_SPEC>`"]
1015pub type PLL0PDEC = crate::Reg<pll0pdec::PLL0PDEC_SPEC>;
1016#[doc = "PLL0 550m P divider"]
1017pub mod pll0pdec;
1018#[doc = "PLL0SSCG0 register accessor: an alias for `Reg<PLL0SSCG0_SPEC>`"]
1019pub type PLL0SSCG0 = crate::Reg<pll0sscg0::PLL0SSCG0_SPEC>;
1020#[doc = "PLL0 Spread Spectrum Wrapper control register 0"]
1021pub mod pll0sscg0;
1022#[doc = "PLL0SSCG1 register accessor: an alias for `Reg<PLL0SSCG1_SPEC>`"]
1023pub type PLL0SSCG1 = crate::Reg<pll0sscg1::PLL0SSCG1_SPEC>;
1024#[doc = "PLL0 Spread Spectrum Wrapper control register 1"]
1025pub mod pll0sscg1;
1026#[doc = "CPUCTRL register accessor: an alias for `Reg<CPUCTRL_SPEC>`"]
1027pub type CPUCTRL = crate::Reg<cpuctrl::CPUCTRL_SPEC>;
1028#[doc = "CPU Control for multiple processors"]
1029pub mod cpuctrl;
1030#[doc = "CPBOOT register accessor: an alias for `Reg<CPBOOT_SPEC>`"]
1031pub type CPBOOT = crate::Reg<cpboot::CPBOOT_SPEC>;
1032#[doc = "Coprocessor Boot Address"]
1033pub mod cpboot;
1034#[doc = "CPSTAT register accessor: an alias for `Reg<CPSTAT_SPEC>`"]
1035pub type CPSTAT = crate::Reg<cpstat::CPSTAT_SPEC>;
1036#[doc = "CPU Status"]
1037pub mod cpstat;
1038#[doc = "CLOCK_CTRL register accessor: an alias for `Reg<CLOCK_CTRL_SPEC>`"]
1039pub type CLOCK_CTRL = crate::Reg<clock_ctrl::CLOCK_CTRL_SPEC>;
1040#[doc = "Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures"]
1041pub mod clock_ctrl;
1042#[doc = "COMP_INT_CTRL register accessor: an alias for `Reg<COMP_INT_CTRL_SPEC>`"]
1043pub type COMP_INT_CTRL = crate::Reg<comp_int_ctrl::COMP_INT_CTRL_SPEC>;
1044#[doc = "Comparator Interrupt control"]
1045pub mod comp_int_ctrl;
1046#[doc = "COMP_INT_STATUS register accessor: an alias for `Reg<COMP_INT_STATUS_SPEC>`"]
1047pub type COMP_INT_STATUS = crate::Reg<comp_int_status::COMP_INT_STATUS_SPEC>;
1048#[doc = "Comparator Interrupt status"]
1049pub mod comp_int_status;
1050#[doc = "AUTOCLKGATEOVERRIDE register accessor: an alias for `Reg<AUTOCLKGATEOVERRIDE_SPEC>`"]
1051pub type AUTOCLKGATEOVERRIDE = crate::Reg<autoclkgateoverride::AUTOCLKGATEOVERRIDE_SPEC>;
1052#[doc = "Control automatic clock gating"]
1053pub mod autoclkgateoverride;
1054#[doc = "GPIOPSYNC register accessor: an alias for `Reg<GPIOPSYNC_SPEC>`"]
1055pub type GPIOPSYNC = crate::Reg<gpiopsync::GPIOPSYNC_SPEC>;
1056#[doc = "Enable bypass of the first stage of synchonization inside GPIO_INT module"]
1057pub mod gpiopsync;
1058#[doc = "DEBUG_LOCK_EN register accessor: an alias for `Reg<DEBUG_LOCK_EN_SPEC>`"]
1059pub type DEBUG_LOCK_EN = crate::Reg<debug_lock_en::DEBUG_LOCK_EN_SPEC>;
1060#[doc = "Control write access to security registers."]
1061pub mod debug_lock_en;
1062#[doc = "DEBUG_FEATURES register accessor: an alias for `Reg<DEBUG_FEATURES_SPEC>`"]
1063pub type DEBUG_FEATURES = crate::Reg<debug_features::DEBUG_FEATURES_SPEC>;
1064#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control."]
1065pub mod debug_features;
1066#[doc = "DEBUG_FEATURES_DP register accessor: an alias for `Reg<DEBUG_FEATURES_DP_SPEC>`"]
1067pub type DEBUG_FEATURES_DP = crate::Reg<debug_features_dp::DEBUG_FEATURES_DP_SPEC>;
1068#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register."]
1069pub mod debug_features_dp;
1070#[doc = "KEY_BLOCK register accessor: an alias for `Reg<KEY_BLOCK_SPEC>`"]
1071pub type KEY_BLOCK = crate::Reg<key_block::KEY_BLOCK_SPEC>;
1072#[doc = "block quiddikey/PUF all index."]
1073pub mod key_block;
1074#[doc = "DEBUG_AUTH_BEACON register accessor: an alias for `Reg<DEBUG_AUTH_BEACON_SPEC>`"]
1075pub type DEBUG_AUTH_BEACON = crate::Reg<debug_auth_beacon::DEBUG_AUTH_BEACON_SPEC>;
1076#[doc = "Debug authentication BEACON register"]
1077pub mod debug_auth_beacon;
1078#[doc = "CPUCFG register accessor: an alias for `Reg<CPUCFG_SPEC>`"]
1079pub type CPUCFG = crate::Reg<cpucfg::CPUCFG_SPEC>;
1080#[doc = "CPUs configuration register"]
1081pub mod cpucfg;
1082#[doc = "DEVICE_ID0 register accessor: an alias for `Reg<DEVICE_ID0_SPEC>`"]
1083pub type DEVICE_ID0 = crate::Reg<device_id0::DEVICE_ID0_SPEC>;
1084#[doc = "Device ID"]
1085pub mod device_id0;
1086#[doc = "DIEID register accessor: an alias for `Reg<DIEID_SPEC>`"]
1087pub type DIEID = crate::Reg<dieid::DIEID_SPEC>;
1088#[doc = "Chip revision ID and Number"]
1089pub mod dieid;