1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - DMA control."]
5 pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
6 #[doc = "0x04 - Interrupt status."]
7 pub intstat: crate::Reg<intstat::INTSTAT_SPEC>,
8 #[doc = "0x08 - SRAM address of the channel configuration table."]
9 pub srambase: crate::Reg<srambase::SRAMBASE_SPEC>,
10 _reserved3: [u8; 0x14],
11 #[doc = "0x20 - Channel Enable read and Set for all DMA channels."]
12 pub enableset0: crate::Reg<enableset0::ENABLESET0_SPEC>,
13 _reserved4: [u8; 0x04],
14 #[doc = "0x28 - Channel Enable Clear for all DMA channels."]
15 pub enableclr0: crate::Reg<enableclr0::ENABLECLR0_SPEC>,
16 _reserved5: [u8; 0x04],
17 #[doc = "0x30 - Channel Active status for all DMA channels."]
18 pub active0: crate::Reg<active0::ACTIVE0_SPEC>,
19 _reserved6: [u8; 0x04],
20 #[doc = "0x38 - Channel Busy status for all DMA channels."]
21 pub busy0: crate::Reg<busy0::BUSY0_SPEC>,
22 _reserved7: [u8; 0x04],
23 #[doc = "0x40 - Error Interrupt status for all DMA channels."]
24 pub errint0: crate::Reg<errint0::ERRINT0_SPEC>,
25 _reserved8: [u8; 0x04],
26 #[doc = "0x48 - Interrupt Enable read and Set for all DMA channels."]
27 pub intenset0: crate::Reg<intenset0::INTENSET0_SPEC>,
28 _reserved9: [u8; 0x04],
29 #[doc = "0x50 - Interrupt Enable Clear for all DMA channels."]
30 pub intenclr0: crate::Reg<intenclr0::INTENCLR0_SPEC>,
31 _reserved10: [u8; 0x04],
32 #[doc = "0x58 - Interrupt A status for all DMA channels."]
33 pub inta0: crate::Reg<inta0::INTA0_SPEC>,
34 _reserved11: [u8; 0x04],
35 #[doc = "0x60 - Interrupt B status for all DMA channels."]
36 pub intb0: crate::Reg<intb0::INTB0_SPEC>,
37 _reserved12: [u8; 0x04],
38 #[doc = "0x68 - Set ValidPending control bits for all DMA channels."]
39 pub setvalid0: crate::Reg<setvalid0::SETVALID0_SPEC>,
40 _reserved13: [u8; 0x04],
41 #[doc = "0x70 - Set Trigger control bits for all DMA channels."]
42 pub settrig0: crate::Reg<settrig0::SETTRIG0_SPEC>,
43 _reserved14: [u8; 0x04],
44 #[doc = "0x78 - Channel Abort control for all DMA channels."]
45 pub abort0: crate::Reg<abort0::ABORT0_SPEC>,
46 _reserved15: [u8; 0x0384],
47 #[doc = "0x400..0x40c - no description available"]
48 pub channel0: CHANNEL,
49 _reserved16: [u8; 0x04],
50 #[doc = "0x410..0x41c - no description available"]
51 pub channel1: CHANNEL,
52 _reserved17: [u8; 0x04],
53 #[doc = "0x420..0x42c - no description available"]
54 pub channel2: CHANNEL,
55 _reserved18: [u8; 0x04],
56 #[doc = "0x430..0x43c - no description available"]
57 pub channel3: CHANNEL,
58 _reserved19: [u8; 0x04],
59 #[doc = "0x440..0x44c - no description available"]
60 pub channel4: CHANNEL,
61 _reserved20: [u8; 0x04],
62 #[doc = "0x450..0x45c - no description available"]
63 pub channel5: CHANNEL,
64 _reserved21: [u8; 0x04],
65 #[doc = "0x460..0x46c - no description available"]
66 pub channel6: CHANNEL,
67 _reserved22: [u8; 0x04],
68 #[doc = "0x470..0x47c - no description available"]
69 pub channel7: CHANNEL,
70 _reserved23: [u8; 0x04],
71 #[doc = "0x480..0x48c - no description available"]
72 pub channel8: CHANNEL,
73 _reserved24: [u8; 0x04],
74 #[doc = "0x490..0x49c - no description available"]
75 pub channel9: CHANNEL,
76 _reserved25: [u8; 0x04],
77 #[doc = "0x4a0..0x4ac - no description available"]
78 pub channel10: CHANNEL,
79 _reserved26: [u8; 0x04],
80 #[doc = "0x4b0..0x4bc - no description available"]
81 pub channel11: CHANNEL,
82 _reserved27: [u8; 0x04],
83 #[doc = "0x4c0..0x4cc - no description available"]
84 pub channel12: CHANNEL,
85 _reserved28: [u8; 0x04],
86 #[doc = "0x4d0..0x4dc - no description available"]
87 pub channel13: CHANNEL,
88 _reserved29: [u8; 0x04],
89 #[doc = "0x4e0..0x4ec - no description available"]
90 pub channel14: CHANNEL,
91 _reserved30: [u8; 0x04],
92 #[doc = "0x4f0..0x4fc - no description available"]
93 pub channel15: CHANNEL,
94 _reserved31: [u8; 0x04],
95 #[doc = "0x500..0x50c - no description available"]
96 pub channel16: CHANNEL,
97 _reserved32: [u8; 0x04],
98 #[doc = "0x510..0x51c - no description available"]
99 pub channel17: CHANNEL,
100 _reserved33: [u8; 0x04],
101 #[doc = "0x520..0x52c - no description available"]
102 pub channel18: CHANNEL,
103 _reserved34: [u8; 0x04],
104 #[doc = "0x530..0x53c - no description available"]
105 pub channel19: CHANNEL,
106 _reserved35: [u8; 0x04],
107 #[doc = "0x540..0x54c - no description available"]
108 pub channel20: CHANNEL,
109 _reserved36: [u8; 0x04],
110 #[doc = "0x550..0x55c - no description available"]
111 pub channel21: CHANNEL,
112 _reserved37: [u8; 0x04],
113 #[doc = "0x560..0x56c - no description available"]
114 pub channel22: CHANNEL,
115}
116#[doc = r"Register block"]
117#[repr(C)]
118pub struct CHANNEL {
119 #[doc = "0x00 - Configuration register for DMA channel ."]
120 pub cfg: crate::Reg<self::channel::cfg::CFG_SPEC>,
121 #[doc = "0x04 - Control and status register for DMA channel ."]
122 pub ctlstat: crate::Reg<self::channel::ctlstat::CTLSTAT_SPEC>,
123 #[doc = "0x08 - Transfer configuration register for DMA channel ."]
124 pub xfercfg: crate::Reg<self::channel::xfercfg::XFERCFG_SPEC>,
125}
126#[doc = r"Register block"]
127#[doc = "no description available"]
128pub mod channel;
129#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
130pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
131#[doc = "DMA control."]
132pub mod ctrl;
133#[doc = "INTSTAT register accessor: an alias for `Reg<INTSTAT_SPEC>`"]
134pub type INTSTAT = crate::Reg<intstat::INTSTAT_SPEC>;
135#[doc = "Interrupt status."]
136pub mod intstat;
137#[doc = "SRAMBASE register accessor: an alias for `Reg<SRAMBASE_SPEC>`"]
138pub type SRAMBASE = crate::Reg<srambase::SRAMBASE_SPEC>;
139#[doc = "SRAM address of the channel configuration table."]
140pub mod srambase;
141#[doc = "ENABLESET0 register accessor: an alias for `Reg<ENABLESET0_SPEC>`"]
142pub type ENABLESET0 = crate::Reg<enableset0::ENABLESET0_SPEC>;
143#[doc = "Channel Enable read and Set for all DMA channels."]
144pub mod enableset0;
145#[doc = "ENABLECLR0 register accessor: an alias for `Reg<ENABLECLR0_SPEC>`"]
146pub type ENABLECLR0 = crate::Reg<enableclr0::ENABLECLR0_SPEC>;
147#[doc = "Channel Enable Clear for all DMA channels."]
148pub mod enableclr0;
149#[doc = "ACTIVE0 register accessor: an alias for `Reg<ACTIVE0_SPEC>`"]
150pub type ACTIVE0 = crate::Reg<active0::ACTIVE0_SPEC>;
151#[doc = "Channel Active status for all DMA channels."]
152pub mod active0;
153#[doc = "BUSY0 register accessor: an alias for `Reg<BUSY0_SPEC>`"]
154pub type BUSY0 = crate::Reg<busy0::BUSY0_SPEC>;
155#[doc = "Channel Busy status for all DMA channels."]
156pub mod busy0;
157#[doc = "ERRINT0 register accessor: an alias for `Reg<ERRINT0_SPEC>`"]
158pub type ERRINT0 = crate::Reg<errint0::ERRINT0_SPEC>;
159#[doc = "Error Interrupt status for all DMA channels."]
160pub mod errint0;
161#[doc = "INTENSET0 register accessor: an alias for `Reg<INTENSET0_SPEC>`"]
162pub type INTENSET0 = crate::Reg<intenset0::INTENSET0_SPEC>;
163#[doc = "Interrupt Enable read and Set for all DMA channels."]
164pub mod intenset0;
165#[doc = "INTENCLR0 register accessor: an alias for `Reg<INTENCLR0_SPEC>`"]
166pub type INTENCLR0 = crate::Reg<intenclr0::INTENCLR0_SPEC>;
167#[doc = "Interrupt Enable Clear for all DMA channels."]
168pub mod intenclr0;
169#[doc = "INTA0 register accessor: an alias for `Reg<INTA0_SPEC>`"]
170pub type INTA0 = crate::Reg<inta0::INTA0_SPEC>;
171#[doc = "Interrupt A status for all DMA channels."]
172pub mod inta0;
173#[doc = "INTB0 register accessor: an alias for `Reg<INTB0_SPEC>`"]
174pub type INTB0 = crate::Reg<intb0::INTB0_SPEC>;
175#[doc = "Interrupt B status for all DMA channels."]
176pub mod intb0;
177#[doc = "SETVALID0 register accessor: an alias for `Reg<SETVALID0_SPEC>`"]
178pub type SETVALID0 = crate::Reg<setvalid0::SETVALID0_SPEC>;
179#[doc = "Set ValidPending control bits for all DMA channels."]
180pub mod setvalid0;
181#[doc = "SETTRIG0 register accessor: an alias for `Reg<SETTRIG0_SPEC>`"]
182pub type SETTRIG0 = crate::Reg<settrig0::SETTRIG0_SPEC>;
183#[doc = "Set Trigger control bits for all DMA channels."]
184pub mod settrig0;
185#[doc = "ABORT0 register accessor: an alias for `Reg<ABORT0_SPEC>`"]
186pub type ABORT0 = crate::Reg<abort0::ABORT0_SPEC>;
187#[doc = "Channel Abort control for all DMA channels."]
188pub mod abort0;