pub struct W(_);
Expand description

Register CTRL writer

Implementations

Bit 1 - For host mode, enables high-speed disconnect detector

Bit 2 - Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode

Bit 3 - Indicates that the device has disconnected in High-Speed mode

Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode

Bit 5 - Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

Bit 8 - Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

Bit 9 - Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line

Bit 10 - Resume IRQ: Indicates that the host is sending a wake-up after suspend

Bit 12 - Indicates that the device is connected

Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY

Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY

Bit 16 - Enable wake-up IRQ: Enables interrupt for the wake-up events.

Bit 17 - Wake-up IRQ: Indicates that there is a wak-eup event

Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended

Bit 21 - Enable DP DM change wake-up: Not for customer use

Bit 23 - Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended

Bit 25 - Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

Bit 26 - Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing

Bit 29 - Used by the PHY to indicate a powered-down state

Bit 30 - Gate UTMI Clocks

Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL_SPEC>>

Writes raw bits to the register.

Trait Implementations

The resulting type after dereferencing.

Dereferences the value.

Mutably dereferences the value.

Performs the conversion.

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The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.