Struct lpc55_pac::syscon::fcclksel7::SEL_W

pub struct SEL_W<'a> { /* private fields */ }

Field SEL writer - Flexcomm Interface 7 clock source select for Fractional Rate Divider.

Implementations

impl<'a> SEL_W<'a>

pub fn variant(self, variant: SEL_A) -> &'a mut W

Writes variant to the field

pub fn enum_0x0(self) -> &'a mut W

Main clock.

pub fn enum_0x1(self) -> &'a mut W

system PLL divided clock.

pub fn enum_0x2(self) -> &'a mut W

FRO 12 MHz clock.

pub fn enum_0x3(self) -> &'a mut W

FRO 96 MHz clock.

pub fn enum_0x4(self) -> &'a mut W

FRO 1MHz clock.

pub fn enum_0x5(self) -> &'a mut W

MCLK clock.

pub fn enum_0x6(self) -> &'a mut W

Oscillator 32 kHz clock.

pub fn enum_0x7(self) -> &'a mut W

No clock.

pub fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field