Expand description
FIFO write data.
Structs
Field EOF writer - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
Field EOT writer - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.
FIFO write data.
Field LEN writer - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data transfer is 16 bits in length.
Register FIFOWR reader
Field RXIGNORE writer - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.
Field TXDATA writer - Transmit data to the FIFO.
Field TXSSEL0_N writer - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
Field TXSSEL1_N writer - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
Field TXSSEL2_N writer - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
Field TXSSEL3_N writer - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
Register FIFOWR writer
Enums
End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.
End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.
Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.
Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.
Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.
Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.
Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.