Struct lpc55_pac::spi0::fifotrig::RXLVL_W

pub struct RXLVL_W<'a> { /* private fields */ }

Field RXLVL writer - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

Implementations

impl<'a> RXLVL_W<'a>

pub unsafe fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field