pub struct DIVVAL_R(_);
Expand description
Field DIVVAL
reader - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.
Methods from Deref<Target = FieldReader<u16, u16>>
sourcepub fn bit_is_clear(&self) -> bool
pub fn bit_is_clear(&self) -> bool
Returns true
if the bit is clear (0).
sourcepub fn bit_is_set(&self) -> bool
pub fn bit_is_set(&self) -> bool
Returns true
if the bit is set (1).
Trait Implementations
Auto Trait Implementations
impl RefUnwindSafe for DIVVAL_R
impl Send for DIVVAL_R
impl Sync for DIVVAL_R
impl Unpin for DIVVAL_R
impl UnwindSafe for DIVVAL_R
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more