Struct lpc55_pac::ahb_secure_ctrl::sec_cpu_int_mask1::W

pub struct W(_);

Register SEC_CPU_INT_MASK1 writer

Implementations

impl W

pub fn gpio_int0_irq4(&mut self) -> GPIO_INT0_IRQ4_W<'_>

Bit 0 - Pin interrupt 4 or pattern match engine slice 4 interrupt.

pub fn gpio_int0_irq5(&mut self) -> GPIO_INT0_IRQ5_W<'_>

Bit 1 - Pin interrupt 5 or pattern match engine slice 5 interrupt.

pub fn gpio_int0_irq6(&mut self) -> GPIO_INT0_IRQ6_W<'_>

Bit 2 - Pin interrupt 6 or pattern match engine slice 6 interrupt.

pub fn gpio_int0_irq7(&mut self) -> GPIO_INT0_IRQ7_W<'_>

Bit 3 - Pin interrupt 7 or pattern match engine slice 7 interrupt.

pub fn ctimer2_irq(&mut self) -> CTIMER2_IRQ_W<'_>

Bit 4 - Standard counter/timer 2 interrupt.

pub fn ctimer4_irq(&mut self) -> CTIMER4_IRQ_W<'_>

Bit 5 - Standard counter/timer 4 interrupt.

pub fn os_event_timer_irq(&mut self) -> OS_EVENT_TIMER_IRQ_W<'_>

Bit 6 - OS Event Timer and OS Event Timer Wakeup interrupts

pub fn reserved0(&mut self) -> RESERVED0_W<'_>

Bit 7 - Reserved. Read value is undefined, only zero should be written.

pub fn reserved1(&mut self) -> RESERVED1_W<'_>

Bit 8 - Reserved. Read value is undefined, only zero should be written.

pub fn reserved2(&mut self) -> RESERVED2_W<'_>

Bit 9 - Reserved. Read value is undefined, only zero should be written.

pub fn sdio_irq(&mut self) -> SDIO_IRQ_W<'_>

Bit 10 - SDIO Controller interrupt.

pub fn reserved3(&mut self) -> RESERVED3_W<'_>

Bit 11 - Reserved. Read value is undefined, only zero should be written.

pub fn reserved4(&mut self) -> RESERVED4_W<'_>

Bit 12 - Reserved. Read value is undefined, only zero should be written.

pub fn reserved5(&mut self) -> RESERVED5_W<'_>

Bit 13 - Reserved. Read value is undefined, only zero should be written.

pub fn usb1_phy_irq(&mut self) -> USB1_PHY_IRQ_W<'_>

Bit 14 - USB High Speed PHY Controller interrupt.

pub fn usb1_irq(&mut self) -> USB1_IRQ_W<'_>

Bit 15 - USB High Speed Controller interrupt.

pub fn usb1_needclk(&mut self) -> USB1_NEEDCLK_W<'_>

Bit 16 - USB High Speed Controller Clock request interrupt.

pub fn sec_hypervisor_call_irq(&mut self) -> SEC_HYPERVISOR_CALL_IRQ_W<'_>

Bit 17 - Secure fault Hyper Visor call interrupt.

pub fn sec_gpio_int0_irq0(&mut self) -> SEC_GPIO_INT0_IRQ0_W<'_>

Bit 18 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt.

pub fn sec_gpio_int0_irq1(&mut self) -> SEC_GPIO_INT0_IRQ1_W<'_>

Bit 19 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt.

pub fn plu_irq(&mut self) -> PLU_IRQ_W<'_>

Bit 20 - Programmable Look-Up Controller interrupt.

pub fn sec_vio_irq(&mut self) -> SEC_VIO_IRQ_W<'_>

Bit 21 - Security Violation interrupt.

pub fn sha_irq(&mut self) -> SHA_IRQ_W<'_>

Bit 22 - HASH-AES interrupt.

pub fn casper_irq(&mut self) -> CASPER_IRQ_W<'_>

Bit 23 - CASPER interrupt.

pub fn pufkey_irq(&mut self) -> PUFKEY_IRQ_W<'_>

Bit 24 - PUF interrupt.

pub fn pq_irq(&mut self) -> PQ_IRQ_W<'_>

Bit 25 - Power Quad interrupt.

pub fn sdma1_irq(&mut self) -> SDMA1_IRQ_W<'_>

Bit 26 - System DMA 1 (Secure) interrupt

pub fn lspi_hs_irq(&mut self) -> LSPI_HS_IRQ_W<'_>

Bit 27 - High Speed SPI interrupt

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SEC_CPU_INT_MASK1_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<SEC_CPU_INT_MASK1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SEC_CPU_INT_MASK1_SPEC>> for W

fn from(writer: W<SEC_CPU_INT_MASK1_SPEC>) -> Self

Performs the conversion.