Struct lpc55_pac::ahb_secure_ctrl::sec_cpu_int_mask0::W

pub struct W(_);

Register SEC_CPU_INT_MASK0 writer

Implementations

impl W

pub fn sys_irq(&mut self) -> SYS_IRQ_W<'_>

Bit 0 - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts

pub fn sdma0_irq(&mut self) -> SDMA0_IRQ_W<'_>

Bit 1 - System DMA 0 (non-secure) interrupt.

pub fn gpio_globalint0_irq(&mut self) -> GPIO_GLOBALINT0_IRQ_W<'_>

Bit 2 - GPIO Group 0 interrupt.

pub fn gpio_globalint1_irq(&mut self) -> GPIO_GLOBALINT1_IRQ_W<'_>

Bit 3 - GPIO Group 1 interrupt.

pub fn gpio_int0_irq0(&mut self) -> GPIO_INT0_IRQ0_W<'_>

Bit 4 - Pin interrupt 0 or pattern match engine slice 0 interrupt.

pub fn gpio_int0_irq1(&mut self) -> GPIO_INT0_IRQ1_W<'_>

Bit 5 - Pin interrupt 1 or pattern match engine slice 1 interrupt.

pub fn gpio_int0_irq2(&mut self) -> GPIO_INT0_IRQ2_W<'_>

Bit 6 - Pin interrupt 2 or pattern match engine slice 2 interrupt.

pub fn gpio_int0_irq3(&mut self) -> GPIO_INT0_IRQ3_W<'_>

Bit 7 - Pin interrupt 3 or pattern match engine slice 3 interrupt.

pub fn utick_irq(&mut self) -> UTICK_IRQ_W<'_>

Bit 8 - Micro Tick Timer interrupt.

pub fn mrt_irq(&mut self) -> MRT_IRQ_W<'_>

Bit 9 - Multi-Rate Timer interrupt.

pub fn ctimer0_irq(&mut self) -> CTIMER0_IRQ_W<'_>

Bit 10 - Standard counter/timer 0 interrupt.

pub fn ctimer1_irq(&mut self) -> CTIMER1_IRQ_W<'_>

Bit 11 - Standard counter/timer 1 interrupt.

pub fn sct_irq(&mut self) -> SCT_IRQ_W<'_>

Bit 12 - SCTimer/PWM interrupt.

pub fn ctimer3_irq(&mut self) -> CTIMER3_IRQ_W<'_>

Bit 13 - Standard counter/timer 3 interrupt.

pub fn flexcomm0_irq(&mut self) -> FLEXCOMM0_IRQ_W<'_>

Bit 14 - Flexcomm 0 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm1_irq(&mut self) -> FLEXCOMM1_IRQ_W<'_>

Bit 15 - Flexcomm 1 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm2_irq(&mut self) -> FLEXCOMM2_IRQ_W<'_>

Bit 16 - Flexcomm 2 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm3_irq(&mut self) -> FLEXCOMM3_IRQ_W<'_>

Bit 17 - Flexcomm 3 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm4_irq(&mut self) -> FLEXCOMM4_IRQ_W<'_>

Bit 18 - Flexcomm 4 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm5_irq(&mut self) -> FLEXCOMM5_IRQ_W<'_>

Bit 19 - Flexcomm 5 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm6_irq(&mut self) -> FLEXCOMM6_IRQ_W<'_>

Bit 20 - Flexcomm 6 interrupt (USART, SPI, I2C, I2S).

pub fn flexcomm7_irq(&mut self) -> FLEXCOMM7_IRQ_W<'_>

Bit 21 - Flexcomm 7 interrupt (USART, SPI, I2C, I2S).

pub fn adc_irq(&mut self) -> ADC_IRQ_W<'_>

Bit 22 - General Purpose ADC interrupt.

pub fn reserved0(&mut self) -> RESERVED0_W<'_>

Bit 23 - Reserved. Read value is undefined, only zero should be written.

pub fn acmp_irq(&mut self) -> ACMP_IRQ_W<'_>

Bit 24 - Analog Comparator interrupt.

pub fn reserved1(&mut self) -> RESERVED1_W<'_>

Bit 25 - Reserved. Read value is undefined, only zero should be written.

pub fn reserved2(&mut self) -> RESERVED2_W<'_>

Bit 26 - Reserved. Read value is undefined, only zero should be written.

pub fn usb0_needclk(&mut self) -> USB0_NEEDCLK_W<'_>

Bit 27 - USB Full Speed Controller Clock request interrupt.

pub fn usb0_irq(&mut self) -> USB0_IRQ_W<'_>

Bit 28 - USB Full Speed Controller interrupt.

pub fn rtc_irq(&mut self) -> RTC_IRQ_W<'_>

Bit 29 - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ

pub fn reserved3(&mut self) -> RESERVED3_W<'_>

Bit 30 - Reserved. Read value is undefined, only zero should be written.

pub fn mailbox_irq(&mut self) -> MAILBOX_IRQ_W<'_>

Bit 31 - Mailbox interrupt.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SEC_CPU_INT_MASK0_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<SEC_CPU_INT_MASK0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SEC_CPU_INT_MASK0_SPEC>> for W

fn from(writer: W<SEC_CPU_INT_MASK0_SPEC>) -> Self

Performs the conversion.