lpc55_pac/syscon/
debug_features_dp.rs

1#[doc = "Register `DEBUG_FEATURES_DP` reader"]
2pub struct R(crate::R<DEBUG_FEATURES_DP_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DEBUG_FEATURES_DP_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DEBUG_FEATURES_DP_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DEBUG_FEATURES_DP_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DEBUG_FEATURES_DP` writer"]
17pub struct W(crate::W<DEBUG_FEATURES_DP_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DEBUG_FEATURES_DP_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DEBUG_FEATURES_DP_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DEBUG_FEATURES_DP_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "CPU0 (CPU0) Invasive debug control:.\n\nValue on reset: 1"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum CPU0_DBGEN_A {
41    #[doc = "1: Any other value than b10: invasive debug is disable."]
42    DISABLE = 1,
43    #[doc = "2: 10: Invasive debug is enabled."]
44    ENABLE = 2,
45}
46impl From<CPU0_DBGEN_A> for u8 {
47    #[inline(always)]
48    fn from(variant: CPU0_DBGEN_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `CPU0_DBGEN` reader - CPU0 (CPU0) Invasive debug control:."]
53pub struct CPU0_DBGEN_R(crate::FieldReader<u8, CPU0_DBGEN_A>);
54impl CPU0_DBGEN_R {
55    #[inline(always)]
56    pub(crate) fn new(bits: u8) -> Self {
57        CPU0_DBGEN_R(crate::FieldReader::new(bits))
58    }
59    #[doc = r"Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> Option<CPU0_DBGEN_A> {
62        match self.bits {
63            1 => Some(CPU0_DBGEN_A::DISABLE),
64            2 => Some(CPU0_DBGEN_A::ENABLE),
65            _ => None,
66        }
67    }
68    #[doc = "Checks if the value of the field is `DISABLE`"]
69    #[inline(always)]
70    pub fn is_disable(&self) -> bool {
71        **self == CPU0_DBGEN_A::DISABLE
72    }
73    #[doc = "Checks if the value of the field is `ENABLE`"]
74    #[inline(always)]
75    pub fn is_enable(&self) -> bool {
76        **self == CPU0_DBGEN_A::ENABLE
77    }
78}
79impl core::ops::Deref for CPU0_DBGEN_R {
80    type Target = crate::FieldReader<u8, CPU0_DBGEN_A>;
81    #[inline(always)]
82    fn deref(&self) -> &Self::Target {
83        &self.0
84    }
85}
86#[doc = "Field `CPU0_DBGEN` writer - CPU0 (CPU0) Invasive debug control:."]
87pub struct CPU0_DBGEN_W<'a> {
88    w: &'a mut W,
89}
90impl<'a> CPU0_DBGEN_W<'a> {
91    #[doc = r"Writes `variant` to the field"]
92    #[inline(always)]
93    pub fn variant(self, variant: CPU0_DBGEN_A) -> &'a mut W {
94        unsafe { self.bits(variant.into()) }
95    }
96    #[doc = "Any other value than b10: invasive debug is disable."]
97    #[inline(always)]
98    pub fn disable(self) -> &'a mut W {
99        self.variant(CPU0_DBGEN_A::DISABLE)
100    }
101    #[doc = "10: Invasive debug is enabled."]
102    #[inline(always)]
103    pub fn enable(self) -> &'a mut W {
104        self.variant(CPU0_DBGEN_A::ENABLE)
105    }
106    #[doc = r"Writes raw bits to the field"]
107    #[inline(always)]
108    pub unsafe fn bits(self, value: u8) -> &'a mut W {
109        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
110        self.w
111    }
112}
113#[doc = "CPU0 Non Invasive debug control:.\n\nValue on reset: 1"]
114#[derive(Clone, Copy, Debug, PartialEq)]
115#[repr(u8)]
116pub enum CPU0_NIDEN_A {
117    #[doc = "1: Any other value than b10: invasive debug is disable."]
118    DISABLE = 1,
119    #[doc = "2: 10: Invasive debug is enabled."]
120    ENABLE = 2,
121}
122impl From<CPU0_NIDEN_A> for u8 {
123    #[inline(always)]
124    fn from(variant: CPU0_NIDEN_A) -> Self {
125        variant as _
126    }
127}
128#[doc = "Field `CPU0_NIDEN` reader - CPU0 Non Invasive debug control:."]
129pub struct CPU0_NIDEN_R(crate::FieldReader<u8, CPU0_NIDEN_A>);
130impl CPU0_NIDEN_R {
131    #[inline(always)]
132    pub(crate) fn new(bits: u8) -> Self {
133        CPU0_NIDEN_R(crate::FieldReader::new(bits))
134    }
135    #[doc = r"Get enumerated values variant"]
136    #[inline(always)]
137    pub fn variant(&self) -> Option<CPU0_NIDEN_A> {
138        match self.bits {
139            1 => Some(CPU0_NIDEN_A::DISABLE),
140            2 => Some(CPU0_NIDEN_A::ENABLE),
141            _ => None,
142        }
143    }
144    #[doc = "Checks if the value of the field is `DISABLE`"]
145    #[inline(always)]
146    pub fn is_disable(&self) -> bool {
147        **self == CPU0_NIDEN_A::DISABLE
148    }
149    #[doc = "Checks if the value of the field is `ENABLE`"]
150    #[inline(always)]
151    pub fn is_enable(&self) -> bool {
152        **self == CPU0_NIDEN_A::ENABLE
153    }
154}
155impl core::ops::Deref for CPU0_NIDEN_R {
156    type Target = crate::FieldReader<u8, CPU0_NIDEN_A>;
157    #[inline(always)]
158    fn deref(&self) -> &Self::Target {
159        &self.0
160    }
161}
162#[doc = "Field `CPU0_NIDEN` writer - CPU0 Non Invasive debug control:."]
163pub struct CPU0_NIDEN_W<'a> {
164    w: &'a mut W,
165}
166impl<'a> CPU0_NIDEN_W<'a> {
167    #[doc = r"Writes `variant` to the field"]
168    #[inline(always)]
169    pub fn variant(self, variant: CPU0_NIDEN_A) -> &'a mut W {
170        unsafe { self.bits(variant.into()) }
171    }
172    #[doc = "Any other value than b10: invasive debug is disable."]
173    #[inline(always)]
174    pub fn disable(self) -> &'a mut W {
175        self.variant(CPU0_NIDEN_A::DISABLE)
176    }
177    #[doc = "10: Invasive debug is enabled."]
178    #[inline(always)]
179    pub fn enable(self) -> &'a mut W {
180        self.variant(CPU0_NIDEN_A::ENABLE)
181    }
182    #[doc = r"Writes raw bits to the field"]
183    #[inline(always)]
184    pub unsafe fn bits(self, value: u8) -> &'a mut W {
185        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
186        self.w
187    }
188}
189#[doc = "CPU0 Secure Invasive debug control:.\n\nValue on reset: 1"]
190#[derive(Clone, Copy, Debug, PartialEq)]
191#[repr(u8)]
192pub enum CPU0_SPIDEN_A {
193    #[doc = "1: Any other value than b10: invasive debug is disable."]
194    DISABLE = 1,
195    #[doc = "2: 10: Invasive debug is enabled."]
196    ENABLE = 2,
197}
198impl From<CPU0_SPIDEN_A> for u8 {
199    #[inline(always)]
200    fn from(variant: CPU0_SPIDEN_A) -> Self {
201        variant as _
202    }
203}
204#[doc = "Field `CPU0_SPIDEN` reader - CPU0 Secure Invasive debug control:."]
205pub struct CPU0_SPIDEN_R(crate::FieldReader<u8, CPU0_SPIDEN_A>);
206impl CPU0_SPIDEN_R {
207    #[inline(always)]
208    pub(crate) fn new(bits: u8) -> Self {
209        CPU0_SPIDEN_R(crate::FieldReader::new(bits))
210    }
211    #[doc = r"Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> Option<CPU0_SPIDEN_A> {
214        match self.bits {
215            1 => Some(CPU0_SPIDEN_A::DISABLE),
216            2 => Some(CPU0_SPIDEN_A::ENABLE),
217            _ => None,
218        }
219    }
220    #[doc = "Checks if the value of the field is `DISABLE`"]
221    #[inline(always)]
222    pub fn is_disable(&self) -> bool {
223        **self == CPU0_SPIDEN_A::DISABLE
224    }
225    #[doc = "Checks if the value of the field is `ENABLE`"]
226    #[inline(always)]
227    pub fn is_enable(&self) -> bool {
228        **self == CPU0_SPIDEN_A::ENABLE
229    }
230}
231impl core::ops::Deref for CPU0_SPIDEN_R {
232    type Target = crate::FieldReader<u8, CPU0_SPIDEN_A>;
233    #[inline(always)]
234    fn deref(&self) -> &Self::Target {
235        &self.0
236    }
237}
238#[doc = "Field `CPU0_SPIDEN` writer - CPU0 Secure Invasive debug control:."]
239pub struct CPU0_SPIDEN_W<'a> {
240    w: &'a mut W,
241}
242impl<'a> CPU0_SPIDEN_W<'a> {
243    #[doc = r"Writes `variant` to the field"]
244    #[inline(always)]
245    pub fn variant(self, variant: CPU0_SPIDEN_A) -> &'a mut W {
246        unsafe { self.bits(variant.into()) }
247    }
248    #[doc = "Any other value than b10: invasive debug is disable."]
249    #[inline(always)]
250    pub fn disable(self) -> &'a mut W {
251        self.variant(CPU0_SPIDEN_A::DISABLE)
252    }
253    #[doc = "10: Invasive debug is enabled."]
254    #[inline(always)]
255    pub fn enable(self) -> &'a mut W {
256        self.variant(CPU0_SPIDEN_A::ENABLE)
257    }
258    #[doc = r"Writes raw bits to the field"]
259    #[inline(always)]
260    pub unsafe fn bits(self, value: u8) -> &'a mut W {
261        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
262        self.w
263    }
264}
265#[doc = "CPU0 Secure Non Invasive debug control:.\n\nValue on reset: 1"]
266#[derive(Clone, Copy, Debug, PartialEq)]
267#[repr(u8)]
268pub enum CPU0_SPNIDEN_A {
269    #[doc = "1: Any other value than b10: invasive debug is disable."]
270    DISABLE = 1,
271    #[doc = "2: 10: Invasive debug is enabled."]
272    ENABLE = 2,
273}
274impl From<CPU0_SPNIDEN_A> for u8 {
275    #[inline(always)]
276    fn from(variant: CPU0_SPNIDEN_A) -> Self {
277        variant as _
278    }
279}
280#[doc = "Field `CPU0_SPNIDEN` reader - CPU0 Secure Non Invasive debug control:."]
281pub struct CPU0_SPNIDEN_R(crate::FieldReader<u8, CPU0_SPNIDEN_A>);
282impl CPU0_SPNIDEN_R {
283    #[inline(always)]
284    pub(crate) fn new(bits: u8) -> Self {
285        CPU0_SPNIDEN_R(crate::FieldReader::new(bits))
286    }
287    #[doc = r"Get enumerated values variant"]
288    #[inline(always)]
289    pub fn variant(&self) -> Option<CPU0_SPNIDEN_A> {
290        match self.bits {
291            1 => Some(CPU0_SPNIDEN_A::DISABLE),
292            2 => Some(CPU0_SPNIDEN_A::ENABLE),
293            _ => None,
294        }
295    }
296    #[doc = "Checks if the value of the field is `DISABLE`"]
297    #[inline(always)]
298    pub fn is_disable(&self) -> bool {
299        **self == CPU0_SPNIDEN_A::DISABLE
300    }
301    #[doc = "Checks if the value of the field is `ENABLE`"]
302    #[inline(always)]
303    pub fn is_enable(&self) -> bool {
304        **self == CPU0_SPNIDEN_A::ENABLE
305    }
306}
307impl core::ops::Deref for CPU0_SPNIDEN_R {
308    type Target = crate::FieldReader<u8, CPU0_SPNIDEN_A>;
309    #[inline(always)]
310    fn deref(&self) -> &Self::Target {
311        &self.0
312    }
313}
314#[doc = "Field `CPU0_SPNIDEN` writer - CPU0 Secure Non Invasive debug control:."]
315pub struct CPU0_SPNIDEN_W<'a> {
316    w: &'a mut W,
317}
318impl<'a> CPU0_SPNIDEN_W<'a> {
319    #[doc = r"Writes `variant` to the field"]
320    #[inline(always)]
321    pub fn variant(self, variant: CPU0_SPNIDEN_A) -> &'a mut W {
322        unsafe { self.bits(variant.into()) }
323    }
324    #[doc = "Any other value than b10: invasive debug is disable."]
325    #[inline(always)]
326    pub fn disable(self) -> &'a mut W {
327        self.variant(CPU0_SPNIDEN_A::DISABLE)
328    }
329    #[doc = "10: Invasive debug is enabled."]
330    #[inline(always)]
331    pub fn enable(self) -> &'a mut W {
332        self.variant(CPU0_SPNIDEN_A::ENABLE)
333    }
334    #[doc = r"Writes raw bits to the field"]
335    #[inline(always)]
336    pub unsafe fn bits(self, value: u8) -> &'a mut W {
337        self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6);
338        self.w
339    }
340}
341#[doc = "CPU1 Invasive debug control:.\n\nValue on reset: 1"]
342#[derive(Clone, Copy, Debug, PartialEq)]
343#[repr(u8)]
344pub enum CPU1_DBGEN_A {
345    #[doc = "1: Any other value than b10: invasive debug is disable."]
346    DISABLE = 1,
347    #[doc = "2: 10: Invasive debug is enabled."]
348    ENABLE = 2,
349}
350impl From<CPU1_DBGEN_A> for u8 {
351    #[inline(always)]
352    fn from(variant: CPU1_DBGEN_A) -> Self {
353        variant as _
354    }
355}
356#[doc = "Field `CPU1_DBGEN` reader - CPU1 Invasive debug control:."]
357pub struct CPU1_DBGEN_R(crate::FieldReader<u8, CPU1_DBGEN_A>);
358impl CPU1_DBGEN_R {
359    #[inline(always)]
360    pub(crate) fn new(bits: u8) -> Self {
361        CPU1_DBGEN_R(crate::FieldReader::new(bits))
362    }
363    #[doc = r"Get enumerated values variant"]
364    #[inline(always)]
365    pub fn variant(&self) -> Option<CPU1_DBGEN_A> {
366        match self.bits {
367            1 => Some(CPU1_DBGEN_A::DISABLE),
368            2 => Some(CPU1_DBGEN_A::ENABLE),
369            _ => None,
370        }
371    }
372    #[doc = "Checks if the value of the field is `DISABLE`"]
373    #[inline(always)]
374    pub fn is_disable(&self) -> bool {
375        **self == CPU1_DBGEN_A::DISABLE
376    }
377    #[doc = "Checks if the value of the field is `ENABLE`"]
378    #[inline(always)]
379    pub fn is_enable(&self) -> bool {
380        **self == CPU1_DBGEN_A::ENABLE
381    }
382}
383impl core::ops::Deref for CPU1_DBGEN_R {
384    type Target = crate::FieldReader<u8, CPU1_DBGEN_A>;
385    #[inline(always)]
386    fn deref(&self) -> &Self::Target {
387        &self.0
388    }
389}
390#[doc = "Field `CPU1_DBGEN` writer - CPU1 Invasive debug control:."]
391pub struct CPU1_DBGEN_W<'a> {
392    w: &'a mut W,
393}
394impl<'a> CPU1_DBGEN_W<'a> {
395    #[doc = r"Writes `variant` to the field"]
396    #[inline(always)]
397    pub fn variant(self, variant: CPU1_DBGEN_A) -> &'a mut W {
398        unsafe { self.bits(variant.into()) }
399    }
400    #[doc = "Any other value than b10: invasive debug is disable."]
401    #[inline(always)]
402    pub fn disable(self) -> &'a mut W {
403        self.variant(CPU1_DBGEN_A::DISABLE)
404    }
405    #[doc = "10: Invasive debug is enabled."]
406    #[inline(always)]
407    pub fn enable(self) -> &'a mut W {
408        self.variant(CPU1_DBGEN_A::ENABLE)
409    }
410    #[doc = r"Writes raw bits to the field"]
411    #[inline(always)]
412    pub unsafe fn bits(self, value: u8) -> &'a mut W {
413        self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
414        self.w
415    }
416}
417#[doc = "CPU1 Non Invasive debug control:.\n\nValue on reset: 1"]
418#[derive(Clone, Copy, Debug, PartialEq)]
419#[repr(u8)]
420pub enum CPU1_NIDEN_A {
421    #[doc = "1: Any other value than b10: invasive debug is disable."]
422    DISABLE = 1,
423    #[doc = "2: 10: Invasive debug is enabled."]
424    ENABLE = 2,
425}
426impl From<CPU1_NIDEN_A> for u8 {
427    #[inline(always)]
428    fn from(variant: CPU1_NIDEN_A) -> Self {
429        variant as _
430    }
431}
432#[doc = "Field `CPU1_NIDEN` reader - CPU1 Non Invasive debug control:."]
433pub struct CPU1_NIDEN_R(crate::FieldReader<u8, CPU1_NIDEN_A>);
434impl CPU1_NIDEN_R {
435    #[inline(always)]
436    pub(crate) fn new(bits: u8) -> Self {
437        CPU1_NIDEN_R(crate::FieldReader::new(bits))
438    }
439    #[doc = r"Get enumerated values variant"]
440    #[inline(always)]
441    pub fn variant(&self) -> Option<CPU1_NIDEN_A> {
442        match self.bits {
443            1 => Some(CPU1_NIDEN_A::DISABLE),
444            2 => Some(CPU1_NIDEN_A::ENABLE),
445            _ => None,
446        }
447    }
448    #[doc = "Checks if the value of the field is `DISABLE`"]
449    #[inline(always)]
450    pub fn is_disable(&self) -> bool {
451        **self == CPU1_NIDEN_A::DISABLE
452    }
453    #[doc = "Checks if the value of the field is `ENABLE`"]
454    #[inline(always)]
455    pub fn is_enable(&self) -> bool {
456        **self == CPU1_NIDEN_A::ENABLE
457    }
458}
459impl core::ops::Deref for CPU1_NIDEN_R {
460    type Target = crate::FieldReader<u8, CPU1_NIDEN_A>;
461    #[inline(always)]
462    fn deref(&self) -> &Self::Target {
463        &self.0
464    }
465}
466#[doc = "Field `CPU1_NIDEN` writer - CPU1 Non Invasive debug control:."]
467pub struct CPU1_NIDEN_W<'a> {
468    w: &'a mut W,
469}
470impl<'a> CPU1_NIDEN_W<'a> {
471    #[doc = r"Writes `variant` to the field"]
472    #[inline(always)]
473    pub fn variant(self, variant: CPU1_NIDEN_A) -> &'a mut W {
474        unsafe { self.bits(variant.into()) }
475    }
476    #[doc = "Any other value than b10: invasive debug is disable."]
477    #[inline(always)]
478    pub fn disable(self) -> &'a mut W {
479        self.variant(CPU1_NIDEN_A::DISABLE)
480    }
481    #[doc = "10: Invasive debug is enabled."]
482    #[inline(always)]
483    pub fn enable(self) -> &'a mut W {
484        self.variant(CPU1_NIDEN_A::ENABLE)
485    }
486    #[doc = r"Writes raw bits to the field"]
487    #[inline(always)]
488    pub unsafe fn bits(self, value: u8) -> &'a mut W {
489        self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
490        self.w
491    }
492}
493impl R {
494    #[doc = "Bits 0:1 - CPU0 (CPU0) Invasive debug control:."]
495    #[inline(always)]
496    pub fn cpu0_dbgen(&self) -> CPU0_DBGEN_R {
497        CPU0_DBGEN_R::new((self.bits & 0x03) as u8)
498    }
499    #[doc = "Bits 2:3 - CPU0 Non Invasive debug control:."]
500    #[inline(always)]
501    pub fn cpu0_niden(&self) -> CPU0_NIDEN_R {
502        CPU0_NIDEN_R::new(((self.bits >> 2) & 0x03) as u8)
503    }
504    #[doc = "Bits 4:5 - CPU0 Secure Invasive debug control:."]
505    #[inline(always)]
506    pub fn cpu0_spiden(&self) -> CPU0_SPIDEN_R {
507        CPU0_SPIDEN_R::new(((self.bits >> 4) & 0x03) as u8)
508    }
509    #[doc = "Bits 6:7 - CPU0 Secure Non Invasive debug control:."]
510    #[inline(always)]
511    pub fn cpu0_spniden(&self) -> CPU0_SPNIDEN_R {
512        CPU0_SPNIDEN_R::new(((self.bits >> 6) & 0x03) as u8)
513    }
514    #[doc = "Bits 8:9 - CPU1 Invasive debug control:."]
515    #[inline(always)]
516    pub fn cpu1_dbgen(&self) -> CPU1_DBGEN_R {
517        CPU1_DBGEN_R::new(((self.bits >> 8) & 0x03) as u8)
518    }
519    #[doc = "Bits 10:11 - CPU1 Non Invasive debug control:."]
520    #[inline(always)]
521    pub fn cpu1_niden(&self) -> CPU1_NIDEN_R {
522        CPU1_NIDEN_R::new(((self.bits >> 10) & 0x03) as u8)
523    }
524}
525impl W {
526    #[doc = "Bits 0:1 - CPU0 (CPU0) Invasive debug control:."]
527    #[inline(always)]
528    pub fn cpu0_dbgen(&mut self) -> CPU0_DBGEN_W {
529        CPU0_DBGEN_W { w: self }
530    }
531    #[doc = "Bits 2:3 - CPU0 Non Invasive debug control:."]
532    #[inline(always)]
533    pub fn cpu0_niden(&mut self) -> CPU0_NIDEN_W {
534        CPU0_NIDEN_W { w: self }
535    }
536    #[doc = "Bits 4:5 - CPU0 Secure Invasive debug control:."]
537    #[inline(always)]
538    pub fn cpu0_spiden(&mut self) -> CPU0_SPIDEN_W {
539        CPU0_SPIDEN_W { w: self }
540    }
541    #[doc = "Bits 6:7 - CPU0 Secure Non Invasive debug control:."]
542    #[inline(always)]
543    pub fn cpu0_spniden(&mut self) -> CPU0_SPNIDEN_W {
544        CPU0_SPNIDEN_W { w: self }
545    }
546    #[doc = "Bits 8:9 - CPU1 Invasive debug control:."]
547    #[inline(always)]
548    pub fn cpu1_dbgen(&mut self) -> CPU1_DBGEN_W {
549        CPU1_DBGEN_W { w: self }
550    }
551    #[doc = "Bits 10:11 - CPU1 Non Invasive debug control:."]
552    #[inline(always)]
553    pub fn cpu1_niden(&mut self) -> CPU1_NIDEN_W {
554        CPU1_NIDEN_W { w: self }
555    }
556    #[doc = "Writes raw bits to the register."]
557    #[inline(always)]
558    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
559        self.0.bits(bits);
560        self
561    }
562}
563#[doc = "Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_features_dp](index.html) module"]
564pub struct DEBUG_FEATURES_DP_SPEC;
565impl crate::RegisterSpec for DEBUG_FEATURES_DP_SPEC {
566    type Ux = u32;
567}
568#[doc = "`read()` method returns [debug_features_dp::R](R) reader structure"]
569impl crate::Readable for DEBUG_FEATURES_DP_SPEC {
570    type Reader = R;
571}
572#[doc = "`write(|w| ..)` method takes [debug_features_dp::W](W) writer structure"]
573impl crate::Writable for DEBUG_FEATURES_DP_SPEC {
574    type Writer = W;
575}
576#[doc = "`reset()` method sets DEBUG_FEATURES_DP to value 0x0555"]
577impl crate::Resettable for DEBUG_FEATURES_DP_SPEC {
578    #[inline(always)]
579    fn reset_value() -> Self::Ux {
580        0x0555
581    }
582}
lpc55_pac/syscon/debug_features_dp.rs

lpc55_pac/syscon/
debug_features_dp.rs
