lpc55_pac/rtc/
subsec.rs

1#[doc = "Register `SUBSEC` reader"]
2pub struct R(crate::R<SUBSEC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SUBSEC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SUBSEC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SUBSEC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SUBSEC` writer"]
17pub struct W(crate::W<SUBSEC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SUBSEC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SUBSEC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SUBSEC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SUBSEC` reader - A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes."]
38pub struct SUBSEC_R(crate::FieldReader<u16, u16>);
39impl SUBSEC_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u16) -> Self {
42        SUBSEC_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for SUBSEC_R {
46    type Target = crate::FieldReader<u16, u16>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52impl R {
53    #[doc = "Bits 0:14 - A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes."]
54    #[inline(always)]
55    pub fn subsec(&self) -> SUBSEC_R {
56        SUBSEC_R::new((self.bits & 0x7fff) as u16)
57    }
58}
59impl W {
60    #[doc = "Writes raw bits to the register."]
61    #[inline(always)]
62    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
63        self.0.bits(bits);
64        self
65    }
66}
67#[doc = "Sub-second counter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subsec](index.html) module"]
68pub struct SUBSEC_SPEC;
69impl crate::RegisterSpec for SUBSEC_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [subsec::R](R) reader structure"]
73impl crate::Readable for SUBSEC_SPEC {
74    type Reader = R;
75}
76#[doc = "`write(|w| ..)` method takes [subsec::W](W) writer structure"]
77impl crate::Writable for SUBSEC_SPEC {
78    type Writer = W;
79}
80#[doc = "`reset()` method sets SUBSEC to value 0"]
81impl crate::Resettable for SUBSEC_SPEC {
82    #[inline(always)]
83    fn reset_value() -> Self::Ux {
84        0
85    }
86}
lpc55_pac/rtc/subsec.rs

lpc55_pac/rtc/
subsec.rs
