lpc55_pac/i2c0/
msttime.rs1#[doc = "Register `MSTTIME` reader"]
2pub struct R(crate::R<MSTTIME_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MSTTIME_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MSTTIME_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MSTTIME_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MSTTIME` writer"]
17pub struct W(crate::W<MSTTIME_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MSTTIME_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MSTTIME_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MSTTIME_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.\n\nValue on reset: 7"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum MSTSCLLOW_A {
41 #[doc = "0: 2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
42 CLOCKS_2 = 0,
43 #[doc = "1: 3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
44 CLOCKS_3 = 1,
45 #[doc = "2: 4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
46 CLOCKS_4 = 2,
47 #[doc = "3: 5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
48 CLOCKS_5 = 3,
49 #[doc = "4: 6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
50 CLOCKS_6 = 4,
51 #[doc = "5: 7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
52 CLOCKS_7 = 5,
53 #[doc = "6: 8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
54 CLOCKS_8 = 6,
55 #[doc = "7: 9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
56 CLOCKS_9 = 7,
57}
58impl From<MSTSCLLOW_A> for u8 {
59 #[inline(always)]
60 fn from(variant: MSTSCLLOW_A) -> Self {
61 variant as _
62 }
63}
64#[doc = "Field `MSTSCLLOW` reader - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
65pub struct MSTSCLLOW_R(crate::FieldReader<u8, MSTSCLLOW_A>);
66impl MSTSCLLOW_R {
67 #[inline(always)]
68 pub(crate) fn new(bits: u8) -> Self {
69 MSTSCLLOW_R(crate::FieldReader::new(bits))
70 }
71 #[doc = r"Get enumerated values variant"]
72 #[inline(always)]
73 pub fn variant(&self) -> MSTSCLLOW_A {
74 match self.bits {
75 0 => MSTSCLLOW_A::CLOCKS_2,
76 1 => MSTSCLLOW_A::CLOCKS_3,
77 2 => MSTSCLLOW_A::CLOCKS_4,
78 3 => MSTSCLLOW_A::CLOCKS_5,
79 4 => MSTSCLLOW_A::CLOCKS_6,
80 5 => MSTSCLLOW_A::CLOCKS_7,
81 6 => MSTSCLLOW_A::CLOCKS_8,
82 7 => MSTSCLLOW_A::CLOCKS_9,
83 _ => unreachable!(),
84 }
85 }
86 #[doc = "Checks if the value of the field is `CLOCKS_2`"]
87 #[inline(always)]
88 pub fn is_clocks_2(&self) -> bool {
89 **self == MSTSCLLOW_A::CLOCKS_2
90 }
91 #[doc = "Checks if the value of the field is `CLOCKS_3`"]
92 #[inline(always)]
93 pub fn is_clocks_3(&self) -> bool {
94 **self == MSTSCLLOW_A::CLOCKS_3
95 }
96 #[doc = "Checks if the value of the field is `CLOCKS_4`"]
97 #[inline(always)]
98 pub fn is_clocks_4(&self) -> bool {
99 **self == MSTSCLLOW_A::CLOCKS_4
100 }
101 #[doc = "Checks if the value of the field is `CLOCKS_5`"]
102 #[inline(always)]
103 pub fn is_clocks_5(&self) -> bool {
104 **self == MSTSCLLOW_A::CLOCKS_5
105 }
106 #[doc = "Checks if the value of the field is `CLOCKS_6`"]
107 #[inline(always)]
108 pub fn is_clocks_6(&self) -> bool {
109 **self == MSTSCLLOW_A::CLOCKS_6
110 }
111 #[doc = "Checks if the value of the field is `CLOCKS_7`"]
112 #[inline(always)]
113 pub fn is_clocks_7(&self) -> bool {
114 **self == MSTSCLLOW_A::CLOCKS_7
115 }
116 #[doc = "Checks if the value of the field is `CLOCKS_8`"]
117 #[inline(always)]
118 pub fn is_clocks_8(&self) -> bool {
119 **self == MSTSCLLOW_A::CLOCKS_8
120 }
121 #[doc = "Checks if the value of the field is `CLOCKS_9`"]
122 #[inline(always)]
123 pub fn is_clocks_9(&self) -> bool {
124 **self == MSTSCLLOW_A::CLOCKS_9
125 }
126}
127impl core::ops::Deref for MSTSCLLOW_R {
128 type Target = crate::FieldReader<u8, MSTSCLLOW_A>;
129 #[inline(always)]
130 fn deref(&self) -> &Self::Target {
131 &self.0
132 }
133}
134#[doc = "Field `MSTSCLLOW` writer - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
135pub struct MSTSCLLOW_W<'a> {
136 w: &'a mut W,
137}
138impl<'a> MSTSCLLOW_W<'a> {
139 #[doc = r"Writes `variant` to the field"]
140 #[inline(always)]
141 pub fn variant(self, variant: MSTSCLLOW_A) -> &'a mut W {
142 self.bits(variant.into())
143 }
144 #[doc = "2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider."]
145 #[inline(always)]
146 pub fn clocks_2(self) -> &'a mut W {
147 self.variant(MSTSCLLOW_A::CLOCKS_2)
148 }
149 #[doc = "3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider."]
150 #[inline(always)]
151 pub fn clocks_3(self) -> &'a mut W {
152 self.variant(MSTSCLLOW_A::CLOCKS_3)
153 }
154 #[doc = "4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider."]
155 #[inline(always)]
156 pub fn clocks_4(self) -> &'a mut W {
157 self.variant(MSTSCLLOW_A::CLOCKS_4)
158 }
159 #[doc = "5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider."]
160 #[inline(always)]
161 pub fn clocks_5(self) -> &'a mut W {
162 self.variant(MSTSCLLOW_A::CLOCKS_5)
163 }
164 #[doc = "6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider."]
165 #[inline(always)]
166 pub fn clocks_6(self) -> &'a mut W {
167 self.variant(MSTSCLLOW_A::CLOCKS_6)
168 }
169 #[doc = "7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider."]
170 #[inline(always)]
171 pub fn clocks_7(self) -> &'a mut W {
172 self.variant(MSTSCLLOW_A::CLOCKS_7)
173 }
174 #[doc = "8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider."]
175 #[inline(always)]
176 pub fn clocks_8(self) -> &'a mut W {
177 self.variant(MSTSCLLOW_A::CLOCKS_8)
178 }
179 #[doc = "9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider."]
180 #[inline(always)]
181 pub fn clocks_9(self) -> &'a mut W {
182 self.variant(MSTSCLLOW_A::CLOCKS_9)
183 }
184 #[doc = r"Writes raw bits to the field"]
185 #[inline(always)]
186 pub fn bits(self, value: u8) -> &'a mut W {
187 self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
188 self.w
189 }
190}
191#[doc = "Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.\n\nValue on reset: 7"]
192#[derive(Clone, Copy, Debug, PartialEq)]
193#[repr(u8)]
194pub enum MSTSCLHIGH_A {
195 #[doc = "0: 2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
196 CLOCKS_2 = 0,
197 #[doc = "1: 3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
198 CLOCKS_3 = 1,
199 #[doc = "2: 4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
200 CLOCKS_4 = 2,
201 #[doc = "3: 5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
202 CLOCKS_5 = 3,
203 #[doc = "4: 6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
204 CLOCKS_6 = 4,
205 #[doc = "5: 7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
206 CLOCKS_7 = 5,
207 #[doc = "6: 8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
208 CLOCKS_8 = 6,
209 #[doc = "7: 9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
210 CLOCKS_9 = 7,
211}
212impl From<MSTSCLHIGH_A> for u8 {
213 #[inline(always)]
214 fn from(variant: MSTSCLHIGH_A) -> Self {
215 variant as _
216 }
217}
218#[doc = "Field `MSTSCLHIGH` reader - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
219pub struct MSTSCLHIGH_R(crate::FieldReader<u8, MSTSCLHIGH_A>);
220impl MSTSCLHIGH_R {
221 #[inline(always)]
222 pub(crate) fn new(bits: u8) -> Self {
223 MSTSCLHIGH_R(crate::FieldReader::new(bits))
224 }
225 #[doc = r"Get enumerated values variant"]
226 #[inline(always)]
227 pub fn variant(&self) -> MSTSCLHIGH_A {
228 match self.bits {
229 0 => MSTSCLHIGH_A::CLOCKS_2,
230 1 => MSTSCLHIGH_A::CLOCKS_3,
231 2 => MSTSCLHIGH_A::CLOCKS_4,
232 3 => MSTSCLHIGH_A::CLOCKS_5,
233 4 => MSTSCLHIGH_A::CLOCKS_6,
234 5 => MSTSCLHIGH_A::CLOCKS_7,
235 6 => MSTSCLHIGH_A::CLOCKS_8,
236 7 => MSTSCLHIGH_A::CLOCKS_9,
237 _ => unreachable!(),
238 }
239 }
240 #[doc = "Checks if the value of the field is `CLOCKS_2`"]
241 #[inline(always)]
242 pub fn is_clocks_2(&self) -> bool {
243 **self == MSTSCLHIGH_A::CLOCKS_2
244 }
245 #[doc = "Checks if the value of the field is `CLOCKS_3`"]
246 #[inline(always)]
247 pub fn is_clocks_3(&self) -> bool {
248 **self == MSTSCLHIGH_A::CLOCKS_3
249 }
250 #[doc = "Checks if the value of the field is `CLOCKS_4`"]
251 #[inline(always)]
252 pub fn is_clocks_4(&self) -> bool {
253 **self == MSTSCLHIGH_A::CLOCKS_4
254 }
255 #[doc = "Checks if the value of the field is `CLOCKS_5`"]
256 #[inline(always)]
257 pub fn is_clocks_5(&self) -> bool {
258 **self == MSTSCLHIGH_A::CLOCKS_5
259 }
260 #[doc = "Checks if the value of the field is `CLOCKS_6`"]
261 #[inline(always)]
262 pub fn is_clocks_6(&self) -> bool {
263 **self == MSTSCLHIGH_A::CLOCKS_6
264 }
265 #[doc = "Checks if the value of the field is `CLOCKS_7`"]
266 #[inline(always)]
267 pub fn is_clocks_7(&self) -> bool {
268 **self == MSTSCLHIGH_A::CLOCKS_7
269 }
270 #[doc = "Checks if the value of the field is `CLOCKS_8`"]
271 #[inline(always)]
272 pub fn is_clocks_8(&self) -> bool {
273 **self == MSTSCLHIGH_A::CLOCKS_8
274 }
275 #[doc = "Checks if the value of the field is `CLOCKS_9`"]
276 #[inline(always)]
277 pub fn is_clocks_9(&self) -> bool {
278 **self == MSTSCLHIGH_A::CLOCKS_9
279 }
280}
281impl core::ops::Deref for MSTSCLHIGH_R {
282 type Target = crate::FieldReader<u8, MSTSCLHIGH_A>;
283 #[inline(always)]
284 fn deref(&self) -> &Self::Target {
285 &self.0
286 }
287}
288#[doc = "Field `MSTSCLHIGH` writer - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
289pub struct MSTSCLHIGH_W<'a> {
290 w: &'a mut W,
291}
292impl<'a> MSTSCLHIGH_W<'a> {
293 #[doc = r"Writes `variant` to the field"]
294 #[inline(always)]
295 pub fn variant(self, variant: MSTSCLHIGH_A) -> &'a mut W {
296 self.bits(variant.into())
297 }
298 #[doc = "2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider."]
299 #[inline(always)]
300 pub fn clocks_2(self) -> &'a mut W {
301 self.variant(MSTSCLHIGH_A::CLOCKS_2)
302 }
303 #[doc = "3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider ."]
304 #[inline(always)]
305 pub fn clocks_3(self) -> &'a mut W {
306 self.variant(MSTSCLHIGH_A::CLOCKS_3)
307 }
308 #[doc = "4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider."]
309 #[inline(always)]
310 pub fn clocks_4(self) -> &'a mut W {
311 self.variant(MSTSCLHIGH_A::CLOCKS_4)
312 }
313 #[doc = "5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider."]
314 #[inline(always)]
315 pub fn clocks_5(self) -> &'a mut W {
316 self.variant(MSTSCLHIGH_A::CLOCKS_5)
317 }
318 #[doc = "6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider."]
319 #[inline(always)]
320 pub fn clocks_6(self) -> &'a mut W {
321 self.variant(MSTSCLHIGH_A::CLOCKS_6)
322 }
323 #[doc = "7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider."]
324 #[inline(always)]
325 pub fn clocks_7(self) -> &'a mut W {
326 self.variant(MSTSCLHIGH_A::CLOCKS_7)
327 }
328 #[doc = "8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider."]
329 #[inline(always)]
330 pub fn clocks_8(self) -> &'a mut W {
331 self.variant(MSTSCLHIGH_A::CLOCKS_8)
332 }
333 #[doc = "9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider."]
334 #[inline(always)]
335 pub fn clocks_9(self) -> &'a mut W {
336 self.variant(MSTSCLHIGH_A::CLOCKS_9)
337 }
338 #[doc = r"Writes raw bits to the field"]
339 #[inline(always)]
340 pub fn bits(self, value: u8) -> &'a mut W {
341 self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
342 self.w
343 }
344}
345impl R {
346 #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
347 #[inline(always)]
348 pub fn mstscllow(&self) -> MSTSCLLOW_R {
349 MSTSCLLOW_R::new((self.bits & 0x07) as u8)
350 }
351 #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
352 #[inline(always)]
353 pub fn mstsclhigh(&self) -> MSTSCLHIGH_R {
354 MSTSCLHIGH_R::new(((self.bits >> 4) & 0x07) as u8)
355 }
356}
357impl W {
358 #[doc = "Bits 0:2 - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW."]
359 #[inline(always)]
360 pub fn mstscllow(&mut self) -> MSTSCLLOW_W {
361 MSTSCLLOW_W { w: self }
362 }
363 #[doc = "Bits 4:6 - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH."]
364 #[inline(always)]
365 pub fn mstsclhigh(&mut self) -> MSTSCLHIGH_W {
366 MSTSCLHIGH_W { w: self }
367 }
368 #[doc = "Writes raw bits to the register."]
369 #[inline(always)]
370 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
371 self.0.bits(bits);
372 self
373 }
374}
375#[doc = "Master timing configuration.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msttime](index.html) module"]
376pub struct MSTTIME_SPEC;
377impl crate::RegisterSpec for MSTTIME_SPEC {
378 type Ux = u32;
379}
380#[doc = "`read()` method returns [msttime::R](R) reader structure"]
381impl crate::Readable for MSTTIME_SPEC {
382 type Reader = R;
383}
384#[doc = "`write(|w| ..)` method takes [msttime::W](W) writer structure"]
385impl crate::Writable for MSTTIME_SPEC {
386 type Writer = W;
387}
388#[doc = "`reset()` method sets MSTTIME to value 0x77"]
389impl crate::Resettable for MSTTIME_SPEC {
390 #[inline(always)]
391 fn reset_value() -> Self::Ux {
392 0x77
393 }
394}