lpc55_pac/
ahb_secure_ctrl.rs1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Security access rules for Flash and ROM slaves."]
5 pub sec_ctrl_flash_rom_slave_rule:
6 crate::Reg<sec_ctrl_flash_rom_slave_rule::SEC_CTRL_FLASH_ROM_SLAVE_RULE_SPEC>,
7 _reserved1: [u8; 0x0c],
8 #[doc = "0x10 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
9 pub sec_ctrl_flash_mem_rule0:
10 crate::Reg<sec_ctrl_flash_mem_rule0::SEC_CTRL_FLASH_MEM_RULE0_SPEC>,
11 #[doc = "0x14 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
12 pub sec_ctrl_flash_mem_rule1:
13 crate::Reg<sec_ctrl_flash_mem_rule1::SEC_CTRL_FLASH_MEM_RULE1_SPEC>,
14 #[doc = "0x18 - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
15 pub sec_ctrl_flash_mem_rule2:
16 crate::Reg<sec_ctrl_flash_mem_rule2::SEC_CTRL_FLASH_MEM_RULE2_SPEC>,
17 _reserved4: [u8; 0x04],
18 #[doc = "0x20 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
19 pub sec_ctrl_rom_mem_rule0: crate::Reg<sec_ctrl_rom_mem_rule0::SEC_CTRL_ROM_MEM_RULE0_SPEC>,
20 #[doc = "0x24 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
21 pub sec_ctrl_rom_mem_rule1: crate::Reg<sec_ctrl_rom_mem_rule1::SEC_CTRL_ROM_MEM_RULE1_SPEC>,
22 #[doc = "0x28 - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
23 pub sec_ctrl_rom_mem_rule2: crate::Reg<sec_ctrl_rom_mem_rule2::SEC_CTRL_ROM_MEM_RULE2_SPEC>,
24 #[doc = "0x2c - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
25 pub sec_ctrl_rom_mem_rule3: crate::Reg<sec_ctrl_rom_mem_rule3::SEC_CTRL_ROM_MEM_RULE3_SPEC>,
26 #[doc = "0x30 - Security access rules for RAMX slaves."]
27 pub sec_ctrl_ramx_slave_rule:
28 crate::Reg<sec_ctrl_ramx_slave_rule::SEC_CTRL_RAMX_SLAVE_RULE_SPEC>,
29 _reserved9: [u8; 0x0c],
30 #[doc = "0x40 - Security access rules for RAMX slaves."]
31 pub sec_ctrl_ramx_mem_rule0: crate::Reg<sec_ctrl_ramx_mem_rule0::SEC_CTRL_RAMX_MEM_RULE0_SPEC>,
32 _reserved10: [u8; 0x0c],
33 #[doc = "0x50 - Security access rules for RAM0 slaves."]
34 pub sec_ctrl_ram0_slave_rule:
35 crate::Reg<sec_ctrl_ram0_slave_rule::SEC_CTRL_RAM0_SLAVE_RULE_SPEC>,
36 _reserved11: [u8; 0x0c],
37 #[doc = "0x60 - Security access rules for RAM0 slaves."]
38 pub sec_ctrl_ram0_mem_rule0: crate::Reg<sec_ctrl_ram0_mem_rule0::SEC_CTRL_RAM0_MEM_RULE0_SPEC>,
39 #[doc = "0x64 - Security access rules for RAM0 slaves."]
40 pub sec_ctrl_ram0_mem_rule1: crate::Reg<sec_ctrl_ram0_mem_rule1::SEC_CTRL_RAM0_MEM_RULE1_SPEC>,
41 _reserved13: [u8; 0x08],
42 #[doc = "0x70 - Security access rules for RAM1 slaves."]
43 pub sec_ctrl_ram1_slave_rule:
44 crate::Reg<sec_ctrl_ram1_slave_rule::SEC_CTRL_RAM1_SLAVE_RULE_SPEC>,
45 _reserved14: [u8; 0x0c],
46 #[doc = "0x80 - Security access rules for RAM1 slaves."]
47 pub sec_ctrl_ram1_mem_rule0: crate::Reg<sec_ctrl_ram1_mem_rule0::SEC_CTRL_RAM1_MEM_RULE0_SPEC>,
48 #[doc = "0x84 - Security access rules for RAM1 slaves."]
49 pub sec_ctrl_ram1_mem_rule1: crate::Reg<sec_ctrl_ram1_mem_rule1::SEC_CTRL_RAM1_MEM_RULE1_SPEC>,
50 _reserved16: [u8; 0x08],
51 #[doc = "0x90 - Security access rules for RAM2 slaves."]
52 pub sec_ctrl_ram2_slave_rule:
53 crate::Reg<sec_ctrl_ram2_slave_rule::SEC_CTRL_RAM2_SLAVE_RULE_SPEC>,
54 _reserved17: [u8; 0x0c],
55 #[doc = "0xa0 - Security access rules for RAM2 slaves."]
56 pub sec_ctrl_ram2_mem_rule0: crate::Reg<sec_ctrl_ram2_mem_rule0::SEC_CTRL_RAM2_MEM_RULE0_SPEC>,
57 #[doc = "0xa4 - Security access rules for RAM2 slaves."]
58 pub sec_ctrl_ram2_mem_rule1: crate::Reg<sec_ctrl_ram2_mem_rule1::SEC_CTRL_RAM2_MEM_RULE1_SPEC>,
59 _reserved19: [u8; 0x08],
60 #[doc = "0xb0 - Security access rules for RAM3 slaves."]
61 pub sec_ctrl_ram3_slave_rule:
62 crate::Reg<sec_ctrl_ram3_slave_rule::SEC_CTRL_RAM3_SLAVE_RULE_SPEC>,
63 _reserved20: [u8; 0x0c],
64 #[doc = "0xc0 - Security access rules for RAM3 slaves."]
65 pub sec_ctrl_ram3_mem_rule0: crate::Reg<sec_ctrl_ram3_mem_rule0::SEC_CTRL_RAM3_MEM_RULE0_SPEC>,
66 #[doc = "0xc4 - Security access rules for RAM3 slaves."]
67 pub sec_ctrl_ram3_mem_rule1: crate::Reg<sec_ctrl_ram3_mem_rule1::SEC_CTRL_RAM3_MEM_RULE1_SPEC>,
68 _reserved22: [u8; 0x08],
69 #[doc = "0xd0 - Security access rules for RAM4 slaves."]
70 pub sec_ctrl_ram4_slave_rule:
71 crate::Reg<sec_ctrl_ram4_slave_rule::SEC_CTRL_RAM4_SLAVE_RULE_SPEC>,
72 _reserved23: [u8; 0x0c],
73 #[doc = "0xe0 - Security access rules for RAM4 slaves."]
74 pub sec_ctrl_ram4_mem_rule0: crate::Reg<sec_ctrl_ram4_mem_rule0::SEC_CTRL_RAM4_MEM_RULE0_SPEC>,
75 _reserved24: [u8; 0x0c],
76 #[doc = "0xf0 - Security access rules for both APB Bridges slaves."]
77 pub sec_ctrl_apb_bridge_slave_rule:
78 crate::Reg<sec_ctrl_apb_bridge_slave_rule::SEC_CTRL_APB_BRIDGE_SLAVE_RULE_SPEC>,
79 _reserved25: [u8; 0x0c],
80 #[doc = "0x100 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
81 pub sec_ctrl_apb_bridge0_mem_ctrl0:
82 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl0::SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SPEC>,
83 #[doc = "0x104 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
84 pub sec_ctrl_apb_bridge0_mem_ctrl1:
85 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl1::SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_SPEC>,
86 #[doc = "0x108 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
87 pub sec_ctrl_apb_bridge0_mem_ctrl2:
88 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl2::SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_SPEC>,
89 _reserved28: [u8; 0x04],
90 #[doc = "0x110 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
91 pub sec_ctrl_apb_bridge1_mem_ctrl0:
92 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl0::SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPEC>,
93 #[doc = "0x114 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
94 pub sec_ctrl_apb_bridge1_mem_ctrl1:
95 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl1::SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_SPEC>,
96 #[doc = "0x118 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
97 pub sec_ctrl_apb_bridge1_mem_ctrl2:
98 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl2::SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_SPEC>,
99 #[doc = "0x11c - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
100 pub sec_ctrl_apb_bridge1_mem_ctrl3:
101 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl3::SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_SPEC>,
102 #[doc = "0x120 - Security access rules for AHB peripherals."]
103 pub sec_ctrl_ahb_port8_slave0_rule:
104 crate::Reg<sec_ctrl_ahb_port8_slave0_rule::SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SPEC>,
105 #[doc = "0x124 - Security access rules for AHB peripherals."]
106 pub sec_ctrl_ahb_port8_slave1_rule:
107 crate::Reg<sec_ctrl_ahb_port8_slave1_rule::SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>,
108 _reserved34: [u8; 0x08],
109 #[doc = "0x130 - Security access rules for AHB peripherals."]
110 pub sec_ctrl_ahb_port9_slave0_rule:
111 crate::Reg<sec_ctrl_ahb_port9_slave0_rule::SEC_CTRL_AHB_PORT9_SLAVE0_RULE_SPEC>,
112 #[doc = "0x134 - Security access rules for AHB peripherals."]
113 pub sec_ctrl_ahb_port9_slave1_rule:
114 crate::Reg<sec_ctrl_ahb_port9_slave1_rule::SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SPEC>,
115 _reserved36: [u8; 0x08],
116 #[doc = "0x140 - Security access rules for AHB peripherals."]
117 pub sec_ctrl_ahb_port10_slave0_rule:
118 crate::Reg<sec_ctrl_ahb_port10_slave0_rule::SEC_CTRL_AHB_PORT10_SLAVE0_RULE_SPEC>,
119 #[doc = "0x144 - Security access rules for AHB peripherals."]
120 pub sec_ctrl_ahb_port10_slave1_rule:
121 crate::Reg<sec_ctrl_ahb_port10_slave1_rule::SEC_CTRL_AHB_PORT10_SLAVE1_RULE_SPEC>,
122 _reserved38: [u8; 0x08],
123 #[doc = "0x150 - Security access rules for AHB_SEC_CTRL_AHB."]
124 pub sec_ctrl_ahb_sec_ctrl_mem_rule:
125 crate::Reg<sec_ctrl_ahb_sec_ctrl_mem_rule::SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_SPEC>,
126 _reserved39: [u8; 0x0c],
127 #[doc = "0x160 - Security access rules for USB High speed RAM slaves."]
128 pub sec_ctrl_usb_hs_slave_rule:
129 crate::Reg<sec_ctrl_usb_hs_slave_rule::SEC_CTRL_USB_HS_SLAVE_RULE_SPEC>,
130 _reserved40: [u8; 0x0c],
131 #[doc = "0x170 - Security access rules for RAM_USB_HS."]
132 pub sec_ctrl_usb_hs_mem_rule:
133 crate::Reg<sec_ctrl_usb_hs_mem_rule::SEC_CTRL_USB_HS_MEM_RULE_SPEC>,
134 _reserved41: [u8; 0x0c8c],
135 #[doc = "0xe00..0xe30 - most recent security violation address for AHB port n"]
136 pub sec_vio_addr: [crate::Reg<sec_vio_addr::SEC_VIO_ADDR_SPEC>; 12],
137 _reserved42: [u8; 0x50],
138 #[doc = "0xe80..0xeb0 - most recent security violation miscellaneous information for AHB port n"]
139 pub sec_vio_misc_info: [crate::Reg<sec_vio_misc_info::SEC_VIO_MISC_INFO_SPEC>; 12],
140 _reserved43: [u8; 0x50],
141 #[doc = "0xf00 - security violation address/information registers valid flags"]
142 pub sec_vio_info_valid: crate::Reg<sec_vio_info_valid::SEC_VIO_INFO_VALID_SPEC>,
143 _reserved44: [u8; 0x7c],
144 #[doc = "0xf80 - Secure GPIO mask for port 0 pins."]
145 pub sec_gpio_mask0: crate::Reg<sec_gpio_mask0::SEC_GPIO_MASK0_SPEC>,
146 #[doc = "0xf84 - Secure GPIO mask for port 1 pins."]
147 pub sec_gpio_mask1: crate::Reg<sec_gpio_mask1::SEC_GPIO_MASK1_SPEC>,
148 _reserved46: [u8; 0x08],
149 #[doc = "0xf90 - Secure Interrupt mask for CPU1"]
150 pub sec_cpu_int_mask0: crate::Reg<sec_cpu_int_mask0::SEC_CPU_INT_MASK0_SPEC>,
151 #[doc = "0xf94 - Secure Interrupt mask for CPU1"]
152 pub sec_cpu_int_mask1: crate::Reg<sec_cpu_int_mask1::SEC_CPU_INT_MASK1_SPEC>,
153 _reserved48: [u8; 0x24],
154 #[doc = "0xfbc - Security General Purpose register access control."]
155 pub sec_mask_lock: crate::Reg<sec_mask_lock::SEC_MASK_LOCK_SPEC>,
156 _reserved49: [u8; 0x10],
157 #[doc = "0xfd0 - master secure level register"]
158 pub master_sec_level: crate::Reg<master_sec_level::MASTER_SEC_LEVEL_SPEC>,
159 #[doc = "0xfd4 - master secure level anti-pole register"]
160 pub master_sec_anti_pol_reg: crate::Reg<master_sec_anti_pol_reg::MASTER_SEC_ANTI_POL_REG_SPEC>,
161 _reserved51: [u8; 0x14],
162 #[doc = "0xfec - Miscalleneous control signals for in Cortex M33 (CPU0)"]
163 pub cpu0_lock_reg: crate::Reg<cpu0_lock_reg::CPU0_LOCK_REG_SPEC>,
164 #[doc = "0xff0 - Miscalleneous control signals for in micro-Cortex M33 (CPU1)"]
165 pub cpu1_lock_reg: crate::Reg<cpu1_lock_reg::CPU1_LOCK_REG_SPEC>,
166 _reserved53: [u8; 0x04],
167 #[doc = "0xff8 - secure control duplicate register"]
168 pub misc_ctrl_dp_reg: crate::Reg<misc_ctrl_dp_reg::MISC_CTRL_DP_REG_SPEC>,
169 #[doc = "0xffc - secure control register"]
170 pub misc_ctrl_reg: crate::Reg<misc_ctrl_reg::MISC_CTRL_REG_SPEC>,
171}
172#[doc = "SEC_CTRL_FLASH_ROM_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_FLASH_ROM_SLAVE_RULE_SPEC>`"]
173pub type SEC_CTRL_FLASH_ROM_SLAVE_RULE =
174 crate::Reg<sec_ctrl_flash_rom_slave_rule::SEC_CTRL_FLASH_ROM_SLAVE_RULE_SPEC>;
175#[doc = "Security access rules for Flash and ROM slaves."]
176pub mod sec_ctrl_flash_rom_slave_rule;
177#[doc = "SEC_CTRL_FLASH_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_FLASH_MEM_RULE0_SPEC>`"]
178pub type SEC_CTRL_FLASH_MEM_RULE0 =
179 crate::Reg<sec_ctrl_flash_mem_rule0::SEC_CTRL_FLASH_MEM_RULE0_SPEC>;
180#[doc = "Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
181pub mod sec_ctrl_flash_mem_rule0;
182#[doc = "SEC_CTRL_FLASH_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_FLASH_MEM_RULE1_SPEC>`"]
183pub type SEC_CTRL_FLASH_MEM_RULE1 =
184 crate::Reg<sec_ctrl_flash_mem_rule1::SEC_CTRL_FLASH_MEM_RULE1_SPEC>;
185#[doc = "Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
186pub mod sec_ctrl_flash_mem_rule1;
187#[doc = "SEC_CTRL_FLASH_MEM_RULE2 register accessor: an alias for `Reg<SEC_CTRL_FLASH_MEM_RULE2_SPEC>`"]
188pub type SEC_CTRL_FLASH_MEM_RULE2 =
189 crate::Reg<sec_ctrl_flash_mem_rule2::SEC_CTRL_FLASH_MEM_RULE2_SPEC>;
190#[doc = "Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total."]
191pub mod sec_ctrl_flash_mem_rule2;
192#[doc = "SEC_CTRL_ROM_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE0_SPEC>`"]
193pub type SEC_CTRL_ROM_MEM_RULE0 = crate::Reg<sec_ctrl_rom_mem_rule0::SEC_CTRL_ROM_MEM_RULE0_SPEC>;
194#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
195pub mod sec_ctrl_rom_mem_rule0;
196#[doc = "SEC_CTRL_ROM_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE1_SPEC>`"]
197pub type SEC_CTRL_ROM_MEM_RULE1 = crate::Reg<sec_ctrl_rom_mem_rule1::SEC_CTRL_ROM_MEM_RULE1_SPEC>;
198#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
199pub mod sec_ctrl_rom_mem_rule1;
200#[doc = "SEC_CTRL_ROM_MEM_RULE2 register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE2_SPEC>`"]
201pub type SEC_CTRL_ROM_MEM_RULE2 = crate::Reg<sec_ctrl_rom_mem_rule2::SEC_CTRL_ROM_MEM_RULE2_SPEC>;
202#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
203pub mod sec_ctrl_rom_mem_rule2;
204#[doc = "SEC_CTRL_ROM_MEM_RULE3 register accessor: an alias for `Reg<SEC_CTRL_ROM_MEM_RULE3_SPEC>`"]
205pub type SEC_CTRL_ROM_MEM_RULE3 = crate::Reg<sec_ctrl_rom_mem_rule3::SEC_CTRL_ROM_MEM_RULE3_SPEC>;
206#[doc = "Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total."]
207pub mod sec_ctrl_rom_mem_rule3;
208#[doc = "SEC_CTRL_RAMX_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAMX_SLAVE_RULE_SPEC>`"]
209pub type SEC_CTRL_RAMX_SLAVE_RULE =
210 crate::Reg<sec_ctrl_ramx_slave_rule::SEC_CTRL_RAMX_SLAVE_RULE_SPEC>;
211#[doc = "Security access rules for RAMX slaves."]
212pub mod sec_ctrl_ramx_slave_rule;
213#[doc = "SEC_CTRL_RAMX_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAMX_MEM_RULE0_SPEC>`"]
214pub type SEC_CTRL_RAMX_MEM_RULE0 =
215 crate::Reg<sec_ctrl_ramx_mem_rule0::SEC_CTRL_RAMX_MEM_RULE0_SPEC>;
216#[doc = "Security access rules for RAMX slaves."]
217pub mod sec_ctrl_ramx_mem_rule0;
218#[doc = "SEC_CTRL_RAM0_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAM0_SLAVE_RULE_SPEC>`"]
219pub type SEC_CTRL_RAM0_SLAVE_RULE =
220 crate::Reg<sec_ctrl_ram0_slave_rule::SEC_CTRL_RAM0_SLAVE_RULE_SPEC>;
221#[doc = "Security access rules for RAM0 slaves."]
222pub mod sec_ctrl_ram0_slave_rule;
223#[doc = "SEC_CTRL_RAM0_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAM0_MEM_RULE0_SPEC>`"]
224pub type SEC_CTRL_RAM0_MEM_RULE0 =
225 crate::Reg<sec_ctrl_ram0_mem_rule0::SEC_CTRL_RAM0_MEM_RULE0_SPEC>;
226#[doc = "Security access rules for RAM0 slaves."]
227pub mod sec_ctrl_ram0_mem_rule0;
228#[doc = "SEC_CTRL_RAM0_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_RAM0_MEM_RULE1_SPEC>`"]
229pub type SEC_CTRL_RAM0_MEM_RULE1 =
230 crate::Reg<sec_ctrl_ram0_mem_rule1::SEC_CTRL_RAM0_MEM_RULE1_SPEC>;
231#[doc = "Security access rules for RAM0 slaves."]
232pub mod sec_ctrl_ram0_mem_rule1;
233#[doc = "SEC_CTRL_RAM1_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAM1_SLAVE_RULE_SPEC>`"]
234pub type SEC_CTRL_RAM1_SLAVE_RULE =
235 crate::Reg<sec_ctrl_ram1_slave_rule::SEC_CTRL_RAM1_SLAVE_RULE_SPEC>;
236#[doc = "Security access rules for RAM1 slaves."]
237pub mod sec_ctrl_ram1_slave_rule;
238#[doc = "SEC_CTRL_RAM1_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAM1_MEM_RULE0_SPEC>`"]
239pub type SEC_CTRL_RAM1_MEM_RULE0 =
240 crate::Reg<sec_ctrl_ram1_mem_rule0::SEC_CTRL_RAM1_MEM_RULE0_SPEC>;
241#[doc = "Security access rules for RAM1 slaves."]
242pub mod sec_ctrl_ram1_mem_rule0;
243#[doc = "SEC_CTRL_RAM1_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_RAM1_MEM_RULE1_SPEC>`"]
244pub type SEC_CTRL_RAM1_MEM_RULE1 =
245 crate::Reg<sec_ctrl_ram1_mem_rule1::SEC_CTRL_RAM1_MEM_RULE1_SPEC>;
246#[doc = "Security access rules for RAM1 slaves."]
247pub mod sec_ctrl_ram1_mem_rule1;
248#[doc = "SEC_CTRL_RAM2_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAM2_SLAVE_RULE_SPEC>`"]
249pub type SEC_CTRL_RAM2_SLAVE_RULE =
250 crate::Reg<sec_ctrl_ram2_slave_rule::SEC_CTRL_RAM2_SLAVE_RULE_SPEC>;
251#[doc = "Security access rules for RAM2 slaves."]
252pub mod sec_ctrl_ram2_slave_rule;
253#[doc = "SEC_CTRL_RAM2_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAM2_MEM_RULE0_SPEC>`"]
254pub type SEC_CTRL_RAM2_MEM_RULE0 =
255 crate::Reg<sec_ctrl_ram2_mem_rule0::SEC_CTRL_RAM2_MEM_RULE0_SPEC>;
256#[doc = "Security access rules for RAM2 slaves."]
257pub mod sec_ctrl_ram2_mem_rule0;
258#[doc = "SEC_CTRL_RAM2_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_RAM2_MEM_RULE1_SPEC>`"]
259pub type SEC_CTRL_RAM2_MEM_RULE1 =
260 crate::Reg<sec_ctrl_ram2_mem_rule1::SEC_CTRL_RAM2_MEM_RULE1_SPEC>;
261#[doc = "Security access rules for RAM2 slaves."]
262pub mod sec_ctrl_ram2_mem_rule1;
263#[doc = "SEC_CTRL_RAM3_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAM3_SLAVE_RULE_SPEC>`"]
264pub type SEC_CTRL_RAM3_SLAVE_RULE =
265 crate::Reg<sec_ctrl_ram3_slave_rule::SEC_CTRL_RAM3_SLAVE_RULE_SPEC>;
266#[doc = "Security access rules for RAM3 slaves."]
267pub mod sec_ctrl_ram3_slave_rule;
268#[doc = "SEC_CTRL_RAM3_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAM3_MEM_RULE0_SPEC>`"]
269pub type SEC_CTRL_RAM3_MEM_RULE0 =
270 crate::Reg<sec_ctrl_ram3_mem_rule0::SEC_CTRL_RAM3_MEM_RULE0_SPEC>;
271#[doc = "Security access rules for RAM3 slaves."]
272pub mod sec_ctrl_ram3_mem_rule0;
273#[doc = "SEC_CTRL_RAM3_MEM_RULE1 register accessor: an alias for `Reg<SEC_CTRL_RAM3_MEM_RULE1_SPEC>`"]
274pub type SEC_CTRL_RAM3_MEM_RULE1 =
275 crate::Reg<sec_ctrl_ram3_mem_rule1::SEC_CTRL_RAM3_MEM_RULE1_SPEC>;
276#[doc = "Security access rules for RAM3 slaves."]
277pub mod sec_ctrl_ram3_mem_rule1;
278#[doc = "SEC_CTRL_RAM4_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_RAM4_SLAVE_RULE_SPEC>`"]
279pub type SEC_CTRL_RAM4_SLAVE_RULE =
280 crate::Reg<sec_ctrl_ram4_slave_rule::SEC_CTRL_RAM4_SLAVE_RULE_SPEC>;
281#[doc = "Security access rules for RAM4 slaves."]
282pub mod sec_ctrl_ram4_slave_rule;
283#[doc = "SEC_CTRL_RAM4_MEM_RULE0 register accessor: an alias for `Reg<SEC_CTRL_RAM4_MEM_RULE0_SPEC>`"]
284pub type SEC_CTRL_RAM4_MEM_RULE0 =
285 crate::Reg<sec_ctrl_ram4_mem_rule0::SEC_CTRL_RAM4_MEM_RULE0_SPEC>;
286#[doc = "Security access rules for RAM4 slaves."]
287pub mod sec_ctrl_ram4_mem_rule0;
288#[doc = "SEC_CTRL_APB_BRIDGE_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE_SLAVE_RULE_SPEC>`"]
289pub type SEC_CTRL_APB_BRIDGE_SLAVE_RULE =
290 crate::Reg<sec_ctrl_apb_bridge_slave_rule::SEC_CTRL_APB_BRIDGE_SLAVE_RULE_SPEC>;
291#[doc = "Security access rules for both APB Bridges slaves."]
292pub mod sec_ctrl_apb_bridge_slave_rule;
293#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SPEC>`"]
294pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 =
295 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl0::SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SPEC>;
296#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
297pub mod sec_ctrl_apb_bridge0_mem_ctrl0;
298#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_SPEC>`"]
299pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 =
300 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl1::SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_SPEC>;
301#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
302pub mod sec_ctrl_apb_bridge0_mem_ctrl1;
303#[doc = "SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_SPEC>`"]
304pub type SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 =
305 crate::Reg<sec_ctrl_apb_bridge0_mem_ctrl2::SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_SPEC>;
306#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total."]
307pub mod sec_ctrl_apb_bridge0_mem_ctrl2;
308#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPEC>`"]
309pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 =
310 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl0::SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPEC>;
311#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
312pub mod sec_ctrl_apb_bridge1_mem_ctrl0;
313#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_SPEC>`"]
314pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 =
315 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl1::SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_SPEC>;
316#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
317pub mod sec_ctrl_apb_bridge1_mem_ctrl1;
318#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_SPEC>`"]
319pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 =
320 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl2::SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_SPEC>;
321#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
322pub mod sec_ctrl_apb_bridge1_mem_ctrl2;
323#[doc = "SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 register accessor: an alias for `Reg<SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_SPEC>`"]
324pub type SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 =
325 crate::Reg<sec_ctrl_apb_bridge1_mem_ctrl3::SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_SPEC>;
326#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total."]
327pub mod sec_ctrl_apb_bridge1_mem_ctrl3;
328#[doc = "SEC_CTRL_AHB_PORT8_SLAVE0_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SPEC>`"]
329pub type SEC_CTRL_AHB_PORT8_SLAVE0_RULE =
330 crate::Reg<sec_ctrl_ahb_port8_slave0_rule::SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SPEC>;
331#[doc = "Security access rules for AHB peripherals."]
332pub mod sec_ctrl_ahb_port8_slave0_rule;
333#[doc = "SEC_CTRL_AHB_PORT8_SLAVE1_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>`"]
334pub type SEC_CTRL_AHB_PORT8_SLAVE1_RULE =
335 crate::Reg<sec_ctrl_ahb_port8_slave1_rule::SEC_CTRL_AHB_PORT8_SLAVE1_RULE_SPEC>;
336#[doc = "Security access rules for AHB peripherals."]
337pub mod sec_ctrl_ahb_port8_slave1_rule;
338#[doc = "SEC_CTRL_AHB_PORT9_SLAVE0_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT9_SLAVE0_RULE_SPEC>`"]
339pub type SEC_CTRL_AHB_PORT9_SLAVE0_RULE =
340 crate::Reg<sec_ctrl_ahb_port9_slave0_rule::SEC_CTRL_AHB_PORT9_SLAVE0_RULE_SPEC>;
341#[doc = "Security access rules for AHB peripherals."]
342pub mod sec_ctrl_ahb_port9_slave0_rule;
343#[doc = "SEC_CTRL_AHB_PORT9_SLAVE1_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SPEC>`"]
344pub type SEC_CTRL_AHB_PORT9_SLAVE1_RULE =
345 crate::Reg<sec_ctrl_ahb_port9_slave1_rule::SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SPEC>;
346#[doc = "Security access rules for AHB peripherals."]
347pub mod sec_ctrl_ahb_port9_slave1_rule;
348#[doc = "SEC_CTRL_AHB_PORT10_SLAVE0_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT10_SLAVE0_RULE_SPEC>`"]
349pub type SEC_CTRL_AHB_PORT10_SLAVE0_RULE =
350 crate::Reg<sec_ctrl_ahb_port10_slave0_rule::SEC_CTRL_AHB_PORT10_SLAVE0_RULE_SPEC>;
351#[doc = "Security access rules for AHB peripherals."]
352pub mod sec_ctrl_ahb_port10_slave0_rule;
353#[doc = "SEC_CTRL_AHB_PORT10_SLAVE1_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_PORT10_SLAVE1_RULE_SPEC>`"]
354pub type SEC_CTRL_AHB_PORT10_SLAVE1_RULE =
355 crate::Reg<sec_ctrl_ahb_port10_slave1_rule::SEC_CTRL_AHB_PORT10_SLAVE1_RULE_SPEC>;
356#[doc = "Security access rules for AHB peripherals."]
357pub mod sec_ctrl_ahb_port10_slave1_rule;
358#[doc = "SEC_CTRL_AHB_SEC_CTRL_MEM_RULE register accessor: an alias for `Reg<SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_SPEC>`"]
359pub type SEC_CTRL_AHB_SEC_CTRL_MEM_RULE =
360 crate::Reg<sec_ctrl_ahb_sec_ctrl_mem_rule::SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_SPEC>;
361#[doc = "Security access rules for AHB_SEC_CTRL_AHB."]
362pub mod sec_ctrl_ahb_sec_ctrl_mem_rule;
363#[doc = "SEC_CTRL_USB_HS_SLAVE_RULE register accessor: an alias for `Reg<SEC_CTRL_USB_HS_SLAVE_RULE_SPEC>`"]
364pub type SEC_CTRL_USB_HS_SLAVE_RULE =
365 crate::Reg<sec_ctrl_usb_hs_slave_rule::SEC_CTRL_USB_HS_SLAVE_RULE_SPEC>;
366#[doc = "Security access rules for USB High speed RAM slaves."]
367pub mod sec_ctrl_usb_hs_slave_rule;
368#[doc = "SEC_CTRL_USB_HS_MEM_RULE register accessor: an alias for `Reg<SEC_CTRL_USB_HS_MEM_RULE_SPEC>`"]
369pub type SEC_CTRL_USB_HS_MEM_RULE =
370 crate::Reg<sec_ctrl_usb_hs_mem_rule::SEC_CTRL_USB_HS_MEM_RULE_SPEC>;
371#[doc = "Security access rules for RAM_USB_HS."]
372pub mod sec_ctrl_usb_hs_mem_rule;
373#[doc = "sec_vio_addr register accessor: an alias for `Reg<SEC_VIO_ADDR_SPEC>`"]
374pub type SEC_VIO_ADDR = crate::Reg<sec_vio_addr::SEC_VIO_ADDR_SPEC>;
375#[doc = "most recent security violation address for AHB port n"]
376pub mod sec_vio_addr;
377#[doc = "sec_vio_misc_info register accessor: an alias for `Reg<SEC_VIO_MISC_INFO_SPEC>`"]
378pub type SEC_VIO_MISC_INFO = crate::Reg<sec_vio_misc_info::SEC_VIO_MISC_INFO_SPEC>;
379#[doc = "most recent security violation miscellaneous information for AHB port n"]
380pub mod sec_vio_misc_info;
381#[doc = "SEC_VIO_INFO_VALID register accessor: an alias for `Reg<SEC_VIO_INFO_VALID_SPEC>`"]
382pub type SEC_VIO_INFO_VALID = crate::Reg<sec_vio_info_valid::SEC_VIO_INFO_VALID_SPEC>;
383#[doc = "security violation address/information registers valid flags"]
384pub mod sec_vio_info_valid;
385#[doc = "SEC_GPIO_MASK0 register accessor: an alias for `Reg<SEC_GPIO_MASK0_SPEC>`"]
386pub type SEC_GPIO_MASK0 = crate::Reg<sec_gpio_mask0::SEC_GPIO_MASK0_SPEC>;
387#[doc = "Secure GPIO mask for port 0 pins."]
388pub mod sec_gpio_mask0;
389#[doc = "SEC_GPIO_MASK1 register accessor: an alias for `Reg<SEC_GPIO_MASK1_SPEC>`"]
390pub type SEC_GPIO_MASK1 = crate::Reg<sec_gpio_mask1::SEC_GPIO_MASK1_SPEC>;
391#[doc = "Secure GPIO mask for port 1 pins."]
392pub mod sec_gpio_mask1;
393#[doc = "SEC_CPU_INT_MASK0 register accessor: an alias for `Reg<SEC_CPU_INT_MASK0_SPEC>`"]
394pub type SEC_CPU_INT_MASK0 = crate::Reg<sec_cpu_int_mask0::SEC_CPU_INT_MASK0_SPEC>;
395#[doc = "Secure Interrupt mask for CPU1"]
396pub mod sec_cpu_int_mask0;
397#[doc = "SEC_CPU_INT_MASK1 register accessor: an alias for `Reg<SEC_CPU_INT_MASK1_SPEC>`"]
398pub type SEC_CPU_INT_MASK1 = crate::Reg<sec_cpu_int_mask1::SEC_CPU_INT_MASK1_SPEC>;
399#[doc = "Secure Interrupt mask for CPU1"]
400pub mod sec_cpu_int_mask1;
401#[doc = "SEC_MASK_LOCK register accessor: an alias for `Reg<SEC_MASK_LOCK_SPEC>`"]
402pub type SEC_MASK_LOCK = crate::Reg<sec_mask_lock::SEC_MASK_LOCK_SPEC>;
403#[doc = "Security General Purpose register access control."]
404pub mod sec_mask_lock;
405#[doc = "MASTER_SEC_LEVEL register accessor: an alias for `Reg<MASTER_SEC_LEVEL_SPEC>`"]
406pub type MASTER_SEC_LEVEL = crate::Reg<master_sec_level::MASTER_SEC_LEVEL_SPEC>;
407#[doc = "master secure level register"]
408pub mod master_sec_level;
409#[doc = "MASTER_SEC_ANTI_POL_REG register accessor: an alias for `Reg<MASTER_SEC_ANTI_POL_REG_SPEC>`"]
410pub type MASTER_SEC_ANTI_POL_REG =
411 crate::Reg<master_sec_anti_pol_reg::MASTER_SEC_ANTI_POL_REG_SPEC>;
412#[doc = "master secure level anti-pole register"]
413pub mod master_sec_anti_pol_reg;
414#[doc = "CPU0_LOCK_REG register accessor: an alias for `Reg<CPU0_LOCK_REG_SPEC>`"]
415pub type CPU0_LOCK_REG = crate::Reg<cpu0_lock_reg::CPU0_LOCK_REG_SPEC>;
416#[doc = "Miscalleneous control signals for in Cortex M33 (CPU0)"]
417pub mod cpu0_lock_reg;
418#[doc = "CPU1_LOCK_REG register accessor: an alias for `Reg<CPU1_LOCK_REG_SPEC>`"]
419pub type CPU1_LOCK_REG = crate::Reg<cpu1_lock_reg::CPU1_LOCK_REG_SPEC>;
420#[doc = "Miscalleneous control signals for in micro-Cortex M33 (CPU1)"]
421pub mod cpu1_lock_reg;
422#[doc = "MISC_CTRL_DP_REG register accessor: an alias for `Reg<MISC_CTRL_DP_REG_SPEC>`"]
423pub type MISC_CTRL_DP_REG = crate::Reg<misc_ctrl_dp_reg::MISC_CTRL_DP_REG_SPEC>;
424#[doc = "secure control duplicate register"]
425pub mod misc_ctrl_dp_reg;
426#[doc = "MISC_CTRL_REG register accessor: an alias for `Reg<MISC_CTRL_REG_SPEC>`"]
427pub type MISC_CTRL_REG = crate::Reg<misc_ctrl_reg::MISC_CTRL_REG_SPEC>;
428#[doc = "secure control register"]
429pub mod misc_ctrl_reg;