Enum lpc55_pac::syscon::fcclksel4::SEL_A [−][src]
#[repr(u8)] pub enum SEL_A { ENUM_0X0, ENUM_0X1, ENUM_0X2, ENUM_0X3, ENUM_0X4, ENUM_0X5, ENUM_0X6, ENUM_0X7, }
Flexcomm Interface 4 clock source select for Fractional Rate Divider.
Value on reset: 7
Variants
0: Main clock.
1: system PLL divided clock.
2: FRO 12 MHz clock.
3: FRO 96 MHz clock.
4: FRO 1MHz clock.
5: MCLK clock.
6: Oscillator 32 kHz clock.
7: No clock.
Trait Implementations
impl Clone for SEL_A
[src]
impl Clone for SEL_A
[src]fn clone(&self) -> SEL_A
[src]
pub fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl StructuralPartialEq for SEL_A
[src]
impl StructuralPartialEq for SEL_A
[src]