Struct lpc55_pac::syscon::fcclksel2::SEL_W [−][src]
pub struct SEL_W<'a> { /* fields omitted */ }
Field SEL
writer - Flexcomm Interface 2 clock source select for Fractional Rate Divider.
Implementations
impl<'a> SEL_W<'a>
[src]
impl<'a> SEL_W<'a>
[src]pub fn variant(self, variant: SEL_A) -> &'a mut W
[src]
Writes variant
to the field
pub fn enum_0x0(self) -> &'a mut W
[src]
Main clock.
pub fn enum_0x1(self) -> &'a mut W
[src]
system PLL divided clock.
pub fn enum_0x2(self) -> &'a mut W
[src]
FRO 12 MHz clock.
pub fn enum_0x3(self) -> &'a mut W
[src]
FRO 96 MHz clock.
pub fn enum_0x4(self) -> &'a mut W
[src]
FRO 1MHz clock.
pub fn enum_0x5(self) -> &'a mut W
[src]
MCLK clock.
pub fn enum_0x6(self) -> &'a mut W
[src]
Oscillator 32 kHz clock.
pub fn enum_0x7(self) -> &'a mut W
[src]
No clock.
pub fn bits(self, value: u8) -> &'a mut W
[src]
Writes raw bits to the field