Enum lpc55_pac::syscon::adcclksel::SEL_A [−][src]
#[repr(u8)] pub enum SEL_A { MAINCLK, PLL0, FRO96, NONE, }
ADC clock source select
Value on reset: 7
Variants
0: Main clk.
1: PLL0 clk.
2: FRO 96 MHZ clk.
4: No clk.
Trait Implementations
impl Clone for SEL_A
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impl Clone for SEL_A
[src]fn clone(&self) -> SEL_A
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pub fn clone_from(&mut self, source: &Self)
1.0.0[src]
impl StructuralPartialEq for SEL_A
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impl StructuralPartialEq for SEL_A
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