Struct lpc55_pac::SYSCON

pub struct SYSCON { /* fields omitted */ }

SYSCON

Implementations

impl SYSCON

pub const PTR: *const RegisterBlock

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn systickclkselx0(&self) -> &Reg<SYSTICKCLKSELX0_SPEC>

0x260 - Peripheral reset control register

pub fn systickclksel0(&self) -> &Reg<SYSTICKCLKSEL0_SPEC>

0x260 - System Tick Timer for CPU0 source select

pub fn systickclkselx1(&self) -> &Reg<SYSTICKCLKSELX1_SPEC>

0x264 - Peripheral reset control register

pub fn systickclksel1(&self) -> &Reg<SYSTICKCLKSEL1_SPEC>

0x264 - System Tick Timer for CPU1 source select

pub fn ctimerclkselx0(&self) -> &Reg<CTIMERCLKSELX0_SPEC>

0x26c - Peripheral reset control register

pub fn ctimerclksel0(&self) -> &Reg<CTIMERCLKSEL0_SPEC>

0x26c - CTimer 0 clock source select

pub fn ctimerclkselx1(&self) -> &Reg<CTIMERCLKSELX1_SPEC>

0x270 - Peripheral reset control register

pub fn ctimerclksel1(&self) -> &Reg<CTIMERCLKSEL1_SPEC>

0x270 - CTimer 1 clock source select

pub fn ctimerclkselx2(&self) -> &Reg<CTIMERCLKSELX2_SPEC>

0x274 - Peripheral reset control register

pub fn ctimerclksel2(&self) -> &Reg<CTIMERCLKSEL2_SPEC>

0x274 - CTimer 2 clock source select

pub fn ctimerclkselx3(&self) -> &Reg<CTIMERCLKSELX3_SPEC>

0x278 - Peripheral reset control register

pub fn ctimerclksel3(&self) -> &Reg<CTIMERCLKSEL3_SPEC>

0x278 - CTimer 3 clock source select

pub fn ctimerclkselx4(&self) -> &Reg<CTIMERCLKSELX4_SPEC>

0x27c - Peripheral reset control register

pub fn ctimerclksel4(&self) -> &Reg<CTIMERCLKSEL4_SPEC>

0x27c - CTimer 4 clock source select

pub fn fcclkselx0(&self) -> &Reg<FCCLKSELX0_SPEC>

0x2b0 - Peripheral reset control register

pub fn fcclksel0(&self) -> &Reg<FCCLKSEL0_SPEC>

0x2b0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider

pub fn fcclkselx1(&self) -> &Reg<FCCLKSELX1_SPEC>

0x2b4 - Peripheral reset control register

pub fn fcclksel1(&self) -> &Reg<FCCLKSEL1_SPEC>

0x2b4 - Flexcomm Interface 1 clock source select for Fractional Rate Divider

pub fn fcclkselx2(&self) -> &Reg<FCCLKSELX2_SPEC>

0x2b8 - Peripheral reset control register

pub fn fcclksel2(&self) -> &Reg<FCCLKSEL2_SPEC>

0x2b8 - Flexcomm Interface 2 clock source select for Fractional Rate Divider

pub fn fcclkselx3(&self) -> &Reg<FCCLKSELX3_SPEC>

0x2bc - Peripheral reset control register

pub fn fcclksel3(&self) -> &Reg<FCCLKSEL3_SPEC>

0x2bc - Flexcomm Interface 3 clock source select for Fractional Rate Divider

pub fn fcclkselx4(&self) -> &Reg<FCCLKSELX4_SPEC>

0x2c0 - Peripheral reset control register

pub fn fcclksel4(&self) -> &Reg<FCCLKSEL4_SPEC>

0x2c0 - Flexcomm Interface 4 clock source select for Fractional Rate Divider

pub fn fcclkselx5(&self) -> &Reg<FCCLKSELX5_SPEC>

0x2c4 - Peripheral reset control register

pub fn fcclksel5(&self) -> &Reg<FCCLKSEL5_SPEC>

0x2c4 - Flexcomm Interface 5 clock source select for Fractional Rate Divider

pub fn fcclkselx6(&self) -> &Reg<FCCLKSELX6_SPEC>

0x2c8 - Peripheral reset control register

pub fn fcclksel6(&self) -> &Reg<FCCLKSEL6_SPEC>

0x2c8 - Flexcomm Interface 6 clock source select for Fractional Rate Divider

pub fn fcclkselx7(&self) -> &Reg<FCCLKSELX7_SPEC>

0x2cc - Peripheral reset control register

pub fn fcclksel7(&self) -> &Reg<FCCLKSEL7_SPEC>

0x2cc - Flexcomm Interface 7 clock source select for Fractional Rate Divider

pub fn flexfrgxctrl0(&self) -> &Reg<FLEXFRGXCTRL0_SPEC>

0x320 - Peripheral reset control register

pub fn flexfrg0ctrl(&self) -> &Reg<FLEXFRG0CTRL_SPEC>

0x320 - Fractional rate divider for flexcomm 0

pub fn flexfrgxctrl1(&self) -> &Reg<FLEXFRGXCTRL1_SPEC>

0x324 - Peripheral reset control register

pub fn flexfrg1ctrl(&self) -> &Reg<FLEXFRG1CTRL_SPEC>

0x324 - Fractional rate divider for flexcomm 1

pub fn flexfrgxctrl2(&self) -> &Reg<FLEXFRGXCTRL2_SPEC>

0x328 - Peripheral reset control register

pub fn flexfrg2ctrl(&self) -> &Reg<FLEXFRG2CTRL_SPEC>

0x328 - Fractional rate divider for flexcomm 2

pub fn flexfrgxctrl3(&self) -> &Reg<FLEXFRGXCTRL3_SPEC>

0x32c - Peripheral reset control register

pub fn flexfrg3ctrl(&self) -> &Reg<FLEXFRG3CTRL_SPEC>

0x32c - Fractional rate divider for flexcomm 3

pub fn flexfrgxctrl4(&self) -> &Reg<FLEXFRGXCTRL4_SPEC>

0x330 - Peripheral reset control register

pub fn flexfrg4ctrl(&self) -> &Reg<FLEXFRG4CTRL_SPEC>

0x330 - Fractional rate divider for flexcomm 4

pub fn flexfrgxctrl5(&self) -> &Reg<FLEXFRGXCTRL5_SPEC>

0x334 - Peripheral reset control register

pub fn flexfrg5ctrl(&self) -> &Reg<FLEXFRG5CTRL_SPEC>

0x334 - Fractional rate divider for flexcomm 5

pub fn flexfrgxctrl6(&self) -> &Reg<FLEXFRGXCTRL6_SPEC>

0x338 - Peripheral reset control register

pub fn flexfrg6ctrl(&self) -> &Reg<FLEXFRG6CTRL_SPEC>

0x338 - Fractional rate divider for flexcomm 6

pub fn flexfrgxctrl7(&self) -> &Reg<FLEXFRGXCTRL7_SPEC>

0x33c - Peripheral reset control register

pub fn flexfrg7ctrl(&self) -> &Reg<FLEXFRG7CTRL_SPEC>

0x33c - Fractional rate divider for flexcomm 7

Trait Implementations

impl Debug for SYSCON

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SYSCON

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SYSCON