Struct lpc55_pac::sct0::dmareq0::W

pub struct W(_);

Register DMAREQ0 writer

Implementations

impl W

pub fn dev_0(&mut self) -> DEV_0_W<'_>

Bits 0:15 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.

pub fn drl0(&mut self) -> DRL0_W<'_>

Bit 30 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers.

pub fn drq0(&mut self) -> DRQ0_W<'_>

Bit 31 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<DMAREQ0_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<DMAREQ0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<DMAREQ0_SPEC>> for W

fn from(writer: W<DMAREQ0_SPEC>) -> Self

Performs the conversion.