Struct lpc55_pac::i2s0::fifotrig::RXLVL_W[][src]

pub struct RXLVL_W<'a> { /* fields omitted */ }

Field RXLVL writer - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level can wake up the device just enough to perform DMA, then return to the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX FIFO has received 16 entries (has become full).

Implementations

impl<'a> RXLVL_W<'a>[src]

pub unsafe fn bits(self, value: u8) -> &'a mut W[src]

Writes raw bits to the field

Auto Trait Implementations

impl<'a> Send for RXLVL_W<'a>

impl<'a> Sync for RXLVL_W<'a>

impl<'a> Unpin for RXLVL_W<'a>

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.