Struct lpc55_pac::hashcrypt::cryptcfg::AESCTRPOS_W [−][src]
pub struct AESCTRPOS_W<'a> { /* fields omitted */ }
Field AESCTRPOS
writer - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other use CTR should use ECB directly and do its own XOR and so on.
Implementations
impl<'a> AESCTRPOS_W<'a>
[src]
impl<'a> AESCTRPOS_W<'a>
[src]Auto Trait Implementations
impl<'a> Send for AESCTRPOS_W<'a>
impl<'a> Send for AESCTRPOS_W<'a>
impl<'a> Sync for AESCTRPOS_W<'a>
impl<'a> Sync for AESCTRPOS_W<'a>
impl<'a> Unpin for AESCTRPOS_W<'a>
impl<'a> Unpin for AESCTRPOS_W<'a>