Struct lpc55_pac::dma0::channel::xfercfg::W [−][src]
pub struct W(_);
Register XFERCFG writer
Implementations
impl W[src]
impl W[src]pub fn cfgvalid(&mut self) -> CFGVALID_W<'_>[src]
Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
pub fn reload(&mut self) -> RELOAD_W<'_>[src]
Bit 1 - Indicates whether the channel’s control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
pub fn swtrig(&mut self) -> SWTRIG_W<'_>[src]
Bit 2 - Software Trigger.
pub fn clrtrig(&mut self) -> CLRTRIG_W<'_>[src]
Bit 3 - Clear Trigger.
pub fn setinta(&mut self) -> SETINTA_W<'_>[src]
Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
pub fn setintb(&mut self) -> SETINTB_W<'_>[src]
Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
pub fn width(&mut self) -> WIDTH_W<'_>[src]
Bits 8:9 - Transfer width used for this DMA channel.
pub fn srcinc(&mut self) -> SRCINC_W<'_>[src]
Bits 12:13 - Determines whether the source address is incremented for each DMA transfer.
pub fn dstinc(&mut self) -> DSTINC_W<'_>[src]
Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer.
pub fn xfercount(&mut self) -> XFERCOUNT_W<'_>[src]
Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed.
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]
Writes raw bits to the register.
Methods from Deref<Target = W<XFERCFG_SPEC>>
Trait Implementations
impl From<W<XFERCFG_SPEC>> for W[src]
impl From<W<XFERCFG_SPEC>> for W[src]